Freescale Semiconductor MC9S12ZVM series, Reference Manual

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Appendix B CPMU Electrical Specifications (VREG, OSC, IRC, PLL)
MC9S12ZVM Family Reference Manual Rev. 1.3
758 Freescale Semiconductor
8 M Low Voltage Interrupt Assert Level
(5)
Low Voltage Interrupt Deassert Level
V
LVIA
V
LVID
4.04
4.19 4.23
4.38 4.40
4.49 V
V
9a M VDDX Low Voltage Reset deassert
(6)
V
LVRXD
— 3.05 3.13 V
9b M VDDX Low Voltage Reset assert
(7)
V
LVRXA
2.95 3.02 — V
10 M Trimmed ACLK output frequency f
ACLK
— 20 — KHz
11 M Trimmed ACLK internal clock
∆
f / f
nominal
(8)
df
ACLK
- 6% — + 6% —
12 D The first period after enabling the counter by APIFE
might be reduced by API start up delay t
sdel
— — 100
µ
s
13 T Temperature Sensor Slope dV
HT
4.8 5.05 5.3 mV/
o
C
14 T Temperature Sensor output voltage (150
o
C) untrimmed V
HT
— 2.25 — V
15 T High Temperature Interrupt Assert
(9)
High Temperature Interrupt Deassert
T
HTIA
T
HTID
120
110 132
122 144
134
o
C
o
C
16 M Bandgap output voltage V
BG
1.14 1.20 1.28 V
17a P Max. Base Current For External PNP (VDDX)
(10)
-40
°
C < T
J
< 150
°
C
I
BCTLMAX
2.3 — — mA
17b C Max. Base Current For External PNP (VDDX)
(10)
150
°
C < T
J
< 175
°
C
I
BCTLMAX
1.5 — — mA
18a P Max. Base Current For External PNP (VDDC)
(10)
-40
°
C < T
J
< 150
°
C
I
BCTLCMAX
2.3 — — mA
18b C Max. Base Current For External PNP (VDDC)
(10)
150
°
C < T
J
< 175
°
C
I
BCTLCMAX
1.5 — — mA
19 D Recovery time from STOP t
STP_REC
— 23 —
µ
s
1. External PNP regulator has a higher regulation point to ensure that the current flows through the PNP when the application
fails to disable the internal regulator byclearing INTXON.
2. Please note that the core current is derived from VDDX
3. Further limitation may apply due to maximum allowable T
J
4. Maximum load current depends on the current gain of the external PNP and available base current
5. LVI is monitored on the VDDA supply domain
6. LVRX is monitored on the VDDX supply domain only active during full performance mode. During reduced performance mode
(stop mode) voltage supervision is solely performed by the POR block monitoring core VDD.
7. For the given maximum load currents and V
SUP
input voltages, the MCU will stay out of reset.
8. The ACLK trimming must be set that the minimum period equals to 0.2ms
9. VREGHTTR=0x88
10. This is the minimum base current that can be guaranteed when the external PNP is delivering maximum current.
Table B-1. Voltage Regulator Electrical Characteristics
(Junction Temperature From –40
°
C To +175
°
C unless otherwise stated)
Note: VDDA and VDDX must be shorted on the application board.
Num C Characteristic Symbol Min Typical Max Unit