Chapter 19 128 KB Flash Module (S12ZFTMRZ128K512V2)
MC9S12ZVM Family Reference Manual Rev. 1.3
696
Freescale Semiconductor
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 19-7. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
6
FDIVLCK
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field in normal mode.
5–0
FDIV[5:0]
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to
Section 19.4.5, “Flash Command Operations
,
”
for more information.
Table 19-8. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
FDIV[5:0]
BUSCLK Frequency
(MHz)
FDIV[5:0]
MIN
(1)
MAX
(2)
MIN
MAX
1.0
1.6
0x00
26.6
27.6
0x1A
1.6
2.6
0x01
27.6
28.6
0x1B
2.6
3.6
0x02
28.6
29.6
0x1C
3.6
4.6
0x03
29.6
30.6
0x1D
4.6
5.6
0x04
30.6
31.6
0x1E
5.6
6.6
0x05
31.6
32.6
0x1F
6.6
7.6
0x06
32.6
33.6
0x20
7.6
8.6
0x07
33.6
34.6
0x21
8.6
9.6
0x08
34.6
35.6
0x22
9.6
10.6
0x09
35.6
36.6
0x23
10.6
11.6
0x0A
36.6
37.6
0x24
11.6
12.6
0x0B
37.6
38.6
0x25
12.6
13.6
0x0C
38.6
39.6
0x26
13.6
14.6
0x0D
39.6
40.6
0x27
14.6
15.6
0x0E
40.6
41.6
0x28
15.6
16.6
0x0F
41.6
42.6
0x29
16.6
17.6
0x10
42.6
43.6
0x2A
17.6
18.6
0x11
43.6
44.6
0x2B
