Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
300
Freescale Semiconductor
8.5.2
Description of Reset Operation
Upon detection of any reset of
, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The internal reset of the MCU remains
asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence.In case the
RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal
reset remains asserted longer.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
.
Figure 8-40. RESET Timing
8.5.3
Oscillator Clock Monitor Reset
If the external oscillator is enabled (OSCE=1)and the oscillator clock monitor reset is enabled (OMRE=1),
then in case of loss of oscillation or the oscillator frequency drops below the failure assert frequency f
CMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V6 generates an Oscillator Clock
Monitor Reset. In Full Stop Mode the external oscillator and the oscillator clock monitor are disabled.
8.5.4
PLL Clock Monitor Reset
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency
f
PMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V6 generates a PLL Clock
Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled.
)
(
)
PLLCLK
512 cycles
256 cycles
S12_CPMU drives
possibly
RESET
driven low
externally
)
(
(
RESET
S12_CPMU releases
f
VCORST
RESET pin low
RESET pin
f
VCORST
