Chapter 8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)
MC9S12ZVM Family Reference Manual Rev. 1.3
Freescale Semiconductor
299
8.4.6.3
PLL Bypassed External Mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid.
2. Enable the external Oscillator (OSCE bit)
3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1)
4. Clear all flags in the CPMUIFLG register to be able to detect any status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
6. Select the Oscillator clock as source of the Bus clock (PLLSEL=0)
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:
•
PLLSEL is set automatically and the Bus clock source is switched back to the PLL clock.
•
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
8.5
Resets
8.5.1
General
All reset sources are listed in
. There is only one reset vector for all these reset sources. Refer
to MCU specification for reset vector address.
Table 8-33. Reset Summary
Reset Source
Local Enable
Power-On Reset (POR)
None
Low Voltage Reset (LVR)
None
External pin RESET
None
PLL Clock Monitor Reset
None
Oscillator Clock Monitor Reset
OSCE Bit in CPMUOSC register and
OMRE Bit in CPMUOSC2 register
COP Reset
CR[2:0] in CPMUCOP register
