Appendix B ADC Electricals
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
789
Appendix B
ADC Electricals
This section describes the characteristics of the analog-to-digital converter.
B.1
ADC Operating Characteristics
The Table B-1 shows conditions under which the ADC operates.
The following constraints exist to obtain full-scale, full range results:
VSSA
VRL
V
IN
VRH
VDDA
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table B-1. ADC Operating Characteristics
B.1.1
Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ADC.
A further factor is that PortAD pins that are configured as output drivers switching.
Supply voltage 4.5V < V
DDA
< 5.5 V, -40
o
C < TJ < 150
o
C
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D Reference potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
—
—
V
DDA
/2
V
DDA
V
V
2
D Voltage difference V
DDX
to V
DDA
VDDX
-0.1
0
0.1
V
3
D Voltage difference V
SSX
to V
SSA
VSSX
–0.1
0
0.1
V
4
C Differential reference voltage
(1)
1. The accuracy is reduced if differential reference voltage is less than 4.50 V
V
RH
-V
RL
3.13
5.0
5.5
V
5
C ADC Clock Frequency (derived from bus clock via the
prescaler bus)
f
ADCCLk
0.25
8.0
MHz
6
C Buffer amplifier turn on time (delay after module
start/recovery from Stop mode)
t
REC
—
—
1
s
7
D ADC disable then re-enable require time
t
DISABLE
—
—
3
Bus
Cycles
8
D
ADC Conversion Period
(2)
10 bit resolution:
8 bit resolution:
2. The minimum time assumes a sample time of 4 ADC clock cycles. The maximum time assumes a sample time of 24 ADC
clock cycles.
N
CONV10
N
CONV8
18
16
38
36
ADC
clock
Cycles
