Freescale Semiconductor MC9S12ZVHL32, Reference Manual

Page: 60 / 874

Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
60 Freescale Semiconductor
— If the BDC is enabled, in Stop mode, the VREG remains in full performance mode and the
CPMU continues operation as in run mode..With BDC enabled and BDCCIS bit set, then all
clocks remain active during Stop mode to allow BDC access to internal peripherals. If the BDC
is enabled and BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks
are disabled. With the BDC enabled during Stop, the VREG full performance mode and clock
activity lead to higher current consumption than with BDC disabled
— If the BDC is enabled in Stop mode, then the voltage monitoring remains enabled.
1.10 Security
The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized
that part of the security must lie with the application code. An extreme example would be application code
that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an
application has the capability of downloading code through a serial port and then executing that code (e.g.
an application containing bootloader code), then this capability could potentially be used to read the
EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this
example, the security of the application could be enhanced by requiring a response authentication before
any code can be downloaded.
Device security details are also described in the flash block description ( Section 21.5, “Security” ).
1.10.1 Features
The security features of the S12Z chip family are:
• Prevent external access of the non-volatile memories (Flash, EEPROM) content
• Restrict execution of NVM commands
1.10.2 Securing the Microcontroller
The chip can be secured by programming the security bits located in the options/security byte in the Flash
memory array. These non-volatile bits keep the device secured through reset and power-down.
This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for
security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a
reset sequence.
The meaning of the security bits SEC[1:0] is shown in Table 1-9 . For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.