Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
397
Please note that there is always a pump phase of two ADC_CLK cycles before the sample phase begins,
hence glitches during the pump phase could impact the conversion accuracy for short sample times.
10.5.3
Digital Sub-Block
The digital sub-block contains a list-based programmer’s model and the control logic for the analog sub-
block circuits.
10.5.3.1
Analog-to-Digital (A/D) Machine
The A/D machine performs the analog-to-digital conversion. The resolution is program selectable to be
either 8- or 10- or 12 bits. The A/D machine uses a successive approximation architecture. It functions by
comparing the sampled and stored analog voltage with a series of binary coded discrete voltages.
By following a binary search algorithm, the A/D machine identifies the discrete voltage that is nearest to
the sampled and stored voltage.
Only analog input signals within the potential range of VRL_0/1 to VRH_0/1 (A/D reference potentials)
will result in a non-railed digital output code.
10.5.3.2
Introduction of the Programmer’s Model
The ADC_LBA provides a programmer’s model that uses a system memory list-based architecture for
definition of the conversion command sequence and conversion result handling.
The Command Sequence List (CSL) and Result Value List (RVL) are implemented in double buffered
manner and the buffer mode is user selectable for each list (bits CSL_BMOD, RVL_BMOD). The 32-bit
wide conversion command is double buffered and the currently active command is visible in the ADC
register map at ADCCMD register space.
