Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
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1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range
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4-20 MHz amplitude controlled pierce oscillator
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32 KHz oscillator for RTC and LCD
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Internal COP (watchdog) module
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LCD driver for segment LCD with 40 frontplanes x 4 backplanes
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Stepper Motor Controller (MC) with drivers for up to 2 motors
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Up to 2 Stepper Stall Detector (SSD) modules (one for each motor)
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Real Time Clock (RTC) support the Hour/Minute/Second function and frequency compensation
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One Analog-to-Digital Converters (ADC) with 10-bit resolution and up to 8 channels available on
external pins
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Two Timer module (TIM) supporting input/output channels that provide a range of 16-bit input
capture & output compare (8 channels)
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One Pulse Width Modulation (PWM) modules with up to 8 x 8-bit channels
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Simple Sound Generation (SSG) for monotonic tone generation
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One Inter-Integrated Circuit (IIC) module
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One Serial Peripheral Interface (SPI) module
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Two Serial Communication Interface (SCI) module supporting LIN 1.3, 2.0, 2.1 and SAE J2602
communications on ZVHY. One serial communication interface (SCI) module with interface to
internal LIN phyiscal layer transceiver (with RX connected to a timer channel for frequency
calibration purposes, if desired) on ZVHL.
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One MSCAN (up to 1 Mbp/s, CAN 2.0 A, B compliant) module
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On-chip Voltage Regulator (VREG) for regulation of input supply and all internal voltages
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Autonomous Periodic Interrupt (API) (combination with cyclic, watchdog)
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Supply voltage sense with low battery warning.
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Chip temperature sensor
1.5
Module Features
The following sections provide more details of the integrated modules.
1.5.1
S12Z Central Processor Unit (CPU)
The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X
CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience & performance
impact of page swapping.
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Harvard Architecture - parallel data and code access
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3 stage pipeline
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32-Bit wide instruction and databus
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32-Bit ALU
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24-bit addressing, i.e. 16 MB linear address space
