Freescale Semiconductor MC9S12ZVHL32, Reference Manual

Page: 205 / 874

Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 205
Table 6-39 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, because matches based on opcodes reaching the execution stage are data independent.
6.3.2.23 Debug Comparator D Address Register (DBGDAH, DBGDAM, DBGDAL)
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
1. If the CDCM field selects range mode comparisons, then DBGCCTL bits configure the comparison, DBGDCTL is ignored.
Table 6-39. Read or Write Comparison Logic Table
RWE Bit RW Bit RW Signal Comment
0 x 0 RW not used in comparison
0 x 1 RW not used in comparison
1 0 0 Write match
1 0 1 No match
1 1 0 No match
1 1 1 Read match
Address: 0x0145, DBGDAH
23 22 21 20 19 18 17 16
R
DBGDA[23:16]
W
Reset 0 0 0 0 0 0 0 0
Address: 0x0146, DBGDAM
15 14 13 12 11 10 9 8
R
DBGDA[15:8]
W
Reset 0 0 0 0 0 0 0 0
Address: 0x0147, DBGDAL
7 6 5 4 3 2 1 0
R
DBGDA[7:0]
W
Reset 0 0 0 0 0 0 0 0
Figure 6-25. Debug Comparator D Address Register
Table 6-40. DBGDAH, DBGDAM, DBGDAL Field Descriptions
Field Description
23–16
DBGDA
[23:16]
Comparator Address Bits [23:16] — These comparator address bits control whether the comparator compares
the address bus bits [23:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one