Chapter 5 Background Debug Controller (S12ZBDCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
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Freescale Semiconductor
STOP Mode With BDC Enabled And BDCCIS Set
If the BDC is enabled and BDCCIS is set, then the BDC prevents core clocks being disabled in stop mode.
This allows BDC communication, for access of internal memory mapped resources, but not CPU registers,
to continue throughout stop mode.
A BACKGROUND command issued whilst in stop mode remains pending internally until the device
leaves stop mode. This means that subsequent active BDM commands, issued whilst BACKGROUND is
pending, set the ILLCMD flag because the device is not yet in active BDM.
If ACK handshaking is enabled, then the first ACK, following a stop mode entry is long to indicate a stop
exception. The BDC indicates a stop mode occurrence by setting the BDCCSR bit STOP. If the host
attempts further communication before the ACK pulse generation then the OVRUN bit is set.
5.1.3.3.2
Wait Mode
The device enters wait mode when the CPU starts to execute the WAI instruction. The second part of the
WAI instruction (return from wait mode) can only be performed when an interrupt occurs. Thus on
entering wait mode the CPU is in the middle of the WAI instruction and cannot permit access to CPU
internal resources, nor allow entry to active BDM. Thus only commands classified as Non-Intrusive or
Always-Available are possible in wait mode.
On entering wait mode, the WAIT flag in BDCCSR is set. If the ACK handshake protocol is enabled then
the first ACK generated after WAIT has been set is a long-ACK pulse. Thus the host can recognize a wait
mode occurrence. The WAIT flag remains set and cannot be cleared whilst the device remains in wait
mode. After the device leaves wait mode the WAIT flag can be cleared by writing a “1” to it.
A BACKGROUND command issued whilst in wait mode sets the NORESP bit and the BDM active
request remains pending internally until the CPU leaves wait mode due to an interrupt. The device then
enters BDM with the PC pointing to the address of the first instruction of the ISR.
With ACK disabled, further Non-Intrusive or Always-Available commands are possible, in this pending
state, but attempted Active-Background commands set NORESP and ILLCMD because the BDC is not in
active BDM state.
With ACK enabled, if the host attempts further communication before the ACK pulse generation then the
OVRUN bit is set.
Similarly the STEP1 command issued from a WAI instruction cannot be completed by the CPU until the
CPU leaves wait mode due to an interrupt. The first STEP1 into wait mode sets the BDCCSR WAIT bit.
If the part is still in Wait mode and a further STEP1 is carried out then the NORESP and ILLCMD bits are
set because the device is no longer in active BDM for the duration of WAI execution.
5.1.4
Block Diagram
