Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
128 Freescale Semiconductor
• One non-maskable unimplemented page2 op-code trap
• One non-maskable software interrupt (SWI)
• One non-maskable system call interrupt (SYS)
• One non-maskable machine exception vector request
• One spurious interrupt vector request
• One system reset vector request
Each of the I-bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. The priority scheme can be used to implement nested interrupt capability where
interrupts from a lower level are automatically blocked if a higher level interrupt is being processed.
4.1.1 Glossary
The following terms and abbreviations are used in the document.
4.1.2 Features
• Interrupt vector base register (IVBR)
• One system reset vector (at address 0xFFFFFC).
• One non-maskable unimplemented page1 op-code trap (SPARE) vector (at address vector base
1
+
0x0001F8).
• One non-maskable unimplemented page2 op-code trap (TRAP) vector (at address vector base
1
+
0x0001F4).
• One non-maskable software interrupt request (SWI) vector (at address vector base
1
+ 0x0001F0).
• One non-maskable system call interrupt request (SYS) vector (at address vector base
1
+
0x00001EC).
• One non-maskable machine exception vector request (at address vector base
1
+ 0x0001E8

.
• One spurious interrupt vector (at address vector base
1
+ 0x0001DC).
• One X-bit maskable interrupt vector request associated with XIRQ (at address vector base
1
+
0x0001D8).
Table 4-2. Terminology
Term Meaning
CCW
Condition Code Register (in the S12Z CPU)
DMA
Direct Memory Access
INT
Interrupt
IPL
Interrupt Processing Level
ISR
Interrupt Service Routine
MCU
Micro-Controller Unit
IRQ
refers to the interrupt request associated with the IRQ pin
XIRQ
refers to the interrupt request associated with the XIRQ pin
1. The vector base is a 24-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as the upper 15 bits of the address) and 0x000 (used as the lower 9 bits of the address).