S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
127
Chapter 4
Interrupt (S12ZINTV0)
4.1
Introduction
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
•
I-bit and X-bit maskable interrupt requests
•
One non-maskable unimplemented page1 op-code trap
Table 4-1. Revision History
Version
Number
Revision
Date
Effective
Date
Description of Changes
V00.01
17 Apr 2009
all
Initial version based on S12XINT V2.06
V00.02
14 Jul 2009
all
Reduce RESET vectors from three to one.
V00.03
05 Oct 2009
all
Removed dedicated ECC machine exception vector and marked vector-table
entry “reserved for future use”.
Added a second illegal op-code vector (to distinguish between SPARE and
TRAP).
V00.04
04 Jun 2010
all
Fixed remaining descriptions of RESET vectors.
Split non-maskable hardware interrupts into XGATE software error and
machine exception requests.
Replaced mentions of CCR (old name from S12X) with CCW (new name).
V00.05
12 Jan 2011
all
Corrected wrong IRQ vector address in some descriptions.
V00.06
22 Mar 2011
all
Added vectors for RAM ECC and NVM ECC machine exceptions. And moved
position to 1E0..1E8.
Moved XGATE error interrupt to vector 1DC.
Remaining vectors accordingly.
Removed illegal address reset as a potential reset source.
V00.07
15 Apr 2011
all
Removed illegal address reset as a potential reset source from Exception
vector table as well. Added the other possible reset sources to the table.
Changed register addresses according to S12Z platform definition.
V00.08
02 May 2011
all
Reduced machine exception vectors to one.
Removed XGATE error interrupt.
Moved Spurious interrupt vector to 1DC.
Moved vector base address to 010 to make room for NVM non-volatile
registers.
V00.09
12 Aug 2011
all
Added: Machine exceptions can cause wake-up from STOP or WAIT
V00.10
21 Feb 2012
all
Corrected reset value for INT_CFADDR register
V00.11
02 Jul 2012
all
Removed references and functions related to XGATE
V00.12
22 May 2013
all
added footnote about availability of “Wake-up from STOP or WAIT by XIRQ
with X bit set” feature