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Freescale Semiconductor MC9S12A128, User Manual

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Freescale Semiconductor MC9S12A128 User Manual Download Page 72

Device User Guide — 9S12DT128DGV2/D V02.16

72

Freescale Semiconductor

2.3.51  PS5 / MOSI0 — Port S I/O Pin 5

PS5 is a general purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.52  PS4 / MISO0 — Port S I/O Pin 4

PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

2.3.53  PS3 / TXD1 — Port S I/O Pin 3

PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 1 (SCI1).

2.3.54  PS2 / RXD1 — Port S I/O Pin 2

PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).

2.3.55  PS1 / TXD0 — Port S I/O Pin 1

PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).

2.3.56  PS0 / RXD0 — Port S I/O Pin 0

PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).

2.3.57  PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]

PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).

2.4  Power Supply Pins

MC9S12DT128 power and ground pins are described below.

Table 2-2  MC9S12DT128 Power and Ground Connection Summary

Mnemonic

Pin Number

Nominal

Voltage

Description

112-pin QFP

VDD1, 2

13, 65

2.5V

Internal power and ground generated by internal regulator

VSS1, 2

14, 66

0V

Summary of Contents for MC9S12A128

Page 1: ...evice User Guide Covers MC9S12DT128E MC9S12DG128E MC9S12DJ128E MC9S12DG128 MC9S12DJ128 MC9S12DB128 MC9S12A128 SC515846 SC515847 SC515848 SC515849 SC101161DT SC101161DG SC101161DJ SC102202 SC102203 SC1...

Page 2: ...y 2002 22 July 2002 Added Pull up columns to signal table example for PLL Filter calculation Thermal values for junction to board and package BGND pin pull up Part Order Information Global Register Ta...

Page 3: ...onfiguration Summary Device specific info on CRG Modified Reduced Wait and Run IDD values Mode of Operation chapter Changed leakage current for ADC inputs down to 1uA Minor modification of PLL frequen...

Page 4: ...res Corrected KWP5 pin name in Fig 2 1 112LQFP pin assignments Corrected pull resistor CTRL reset states for PE7 and PE4 PE0 in Table 2 1 Signal Properties Mentioned S12LRAE bootloader in Flash sectio...

Page 5: ...list of A128 in Table 0 1 Derivative Differences V02 14 28 Apr 2005 28 Apr 2005 Updated cover page Added part numbers SC101161DT SC101161DG SC101161DJ SC102202 SC102203 SC102204 SC102205 Added maskset...

Page 6: ...Device User Guide 9S12DT128DGV2 D V02 16 6 Freescale Semiconductor...

Page 7: ...3 5 BKGD TAGHI MODC Background Debug Tag High and Mode Pin 64 2 3 6 PAD 15 AN1 7 ETRIG1 Port AD Input Pin 15 65 2 3 7 PAD 14 8 AN1 6 0 Port AD Input Pins 14 8 65 2 3 8 PAD 7 AN0 7 ETRIG0 Port AD Inpu...

Page 8: ...Port M I O Pin 5 69 2 3 36 PM4 BF_PSYN RXCAN0 RXCAN4 MOSI0 Port M I O Pin 4 70 2 3 37 PM3 TX_BF TXCAN1 TXCAN0 SS0 Port M I O Pin 3 70 2 3 38 PM2 RX_BF RXCAN1 RXCAN0 MISO0 Port M I O Pin 2 70 2 3 39 P...

Page 9: ...SSPLL Power Supply Pins for PLL 74 2 4 7 VREGEN On Chip Voltage Regulator Enable 74 Section 3 System Clock Description 3 1 Overview 75 Section 4 Modes of Operation 4 1 Overview 77 4 2 Chip Configurati...

Page 10: ...nerator CRG Block Description 7 1 Device specific information 86 Section 8 Oscillator OSC Block Description 8 1 Device specific information 86 Section 9 Enhanced Capture Timer ECT Block Description Se...

Page 11: ...bsolute Maximum Ratings 99 A 1 6 ESD Protection and Latch up Immunity 99 A 1 7 Operating Conditions 100 A 1 8 Power Dissipation and Thermal Characteristics 101 A 1 9 I O Characteristics 103 A 1 10 Sup...

Page 12: ...12DT128DGV2 D V02 16 12 Freescale Semiconductor A 8 External Bus Timing 133 A 8 1 General Multiplexed Bus Timing 133 Appendix B Package Information B 1 General 137 B 2 112 pin LQFP package 138 B 3 80...

Page 13: ...7 External Clock Connections PE7 0 66 Figure 3 1 Clock Connections 75 Figure 23 1 Recommended PCB Layout for 112LQFP Colpitts Oscillator 91 Figure 23 2 Recommended PCB Layout for 80QFP MC9S12DG128E MC...

Page 14: ...Device User Guide 9S12DT128DGV2 D V02 16 14 Freescale Semiconductor Figure A 10 General External Bus Timing 134 Figure 23 6 112 pin LQFP mechanical dimensions case no 987 138...

Page 15: ...34 0028 002F BKP HCS12 Breakpoint 34 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control 34 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface 34 0034 003F CRG Clock and Reset Genera...

Page 16: ...Vector Locations 81 Table 23 1 Suggested External Component Values 89 Table A 1 Absolute Maximum Ratings 99 Table A 2 ESD and Latch up Test Conditions 100 Table A 3 ESD and Latch Up Protection Charact...

Page 17: ...Device User Guide 9S12DT128DGV2 D V02 16 17 Freescale Semiconductor Table A 19 SPI Slave Mode Timing Characteristics 132 Table A 20 Expanded Bus Timing Characteristics 135...

Page 18: ...Device User Guide 9S12DT128DGV2 D V02 16 18 Freescale Semiconductor...

Page 19: ...28E3 MC9S12DJ128 SC5158484 SC101161DJ5 SC1022046 MC9S12A128 of CANs 3 2 2 0 CAN4 CAN1 CAN0 J1850 BDLC IIC Byteflight Package 112 LQFP 112 LQFP 80 QFP2 112 LQFP 80 QFP2 112 LQFP 80 QFP2 Package Code PV...

Page 20: ...read CAN0 registers after reset address range 0140 017F if using a derivative without CAN0 see Table 0 1 and Table 0 2 Do not write or read CAN1 registers after reset address range 0180 01BF if using...

Page 21: ...able 0 2 Ports The CAN0 pin functionality TXCAN0 RXCAN0 is not available on port PJ7 PJ6 PM5 PM4 PM3 PM2 PM1 and PM0 if using a derivative without CAN0 see Table 0 1 and Table 0 2 The CAN1 pin functio...

Page 22: ...as outputs or their pull resistors must be enabled to avoid floating inputs PAD 15 8 ATD1 channels Out of reset the ATD1 is disabled preventing current flows in the pins Do not modify the ATD1 regist...

Page 23: ...HCS12 Module Mapping Control MMC Block Guide V04 S12MMCV4 D HCS12 Multiplexed External Bus Interface MEBI Block Guide V03 S12MEBIV3 D HCS12 Interrupt INT Block Guide V01 S12INTV1 D HCS12 Background D...

Page 24: ...Device User Guide 9S12DT128DGV2 D V02 16 24 Freescale Semiconductor...

Page 25: ...oftware compatible modules MSCAN12 a Byteflight module and an Inter IC Bus The MC9S12DT128 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single...

Page 26: ...ror and wake up Low pass filter wake up function Loop back for self test operation Enhanced Capture Timer 16 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channe...

Page 27: ...lines with 5V input and drive capability 5V A D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single wire background debug mode On chip hardware breakpoints 1...

Page 28: ...Device User Guide 9S12DT128DGV2 D V02 16 28 Freescale Semiconductor 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DT128 device...

Page 29: ...1 AN2 AN6 AN0 AN7 AN1 AN3 AN4 AN5 PAD11 PAD12 PAD13 PAD14 PAD15 PAD08 PAD09 PAD10 VDDA VSSA RXD TXD MISO MOSI PS3 PS4 PS5 PS0 PS1 PS2 SCI1 RXD TXD PWM2 PWM6 PWM0 PWM7 PWM1 PWM3 PWM4 PWM5 PP3 PP4 PP5 P...

Page 30: ...bit 8 channels ATD0 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interface SCI0 8 00D0 00D7 Serial Communications Interface SCI1 8 00D8 00DF Serial Perip...

Page 31: ...SINGLE CHIP VECTORS VECTORS VECTORS FF00 FFFF BDM If Active C000 FFFF 16K Fixed Flash EEPROM 2K 4K 8K or 16K Protected Boot Sector 8000 BFFF 16K Page Window eight 16K Flash EEPROM Pages 4000 7FFF 16K...

Page 32: ...PORTE Read Bit 7 6 5 4 3 2 Bit 1 Bit 0 Write 0009 DDRE Read Bit 7 6 5 4 3 Bit 2 0 0 Write 000A PEAR Read NOACCE 0 PIPOE NECLK LSTRE RDWE 0 0 Write 000B MODE Read MODC MODB MODA 0 IVIS 0 EMK EME Write...

Page 33: ...it 2 Bit 1 Bit 0 0018 0019 Reserved Read 0 0 0 0 0 0 0 0 Write 001A 001B Device ID Register Table 1 3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 001A PARTIDH Read ID15 ID14 ID13 ID12...

Page 34: ...K1RWE BK1RW Write 002A BKP0X Read 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write 002B BKP0H Read Bit 15 14 13 12 11 10 9 Bit 8 Write 002C BKP0L Read Bit 7 6 5 4 3 2 1 Bit 0 Write 002D BKP1X Read 0 0 BK...

Page 35: ...Write 003D FORBYP TEST ONLY Read 0 0 0 0 0 0 0 0 Write 003E CTCTL TEST ONLY Read 0 0 0 0 0 0 0 0 Write 003F ARMCOP Read 0 0 0 0 0 0 0 0 Write Bit 7 6 5 4 3 2 1 Bit 0 0040 007F ECT Enhanced Capture Tim...

Page 36: ...1 10 9 Bit 8 Write 0055 TC2 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0056 TC3 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0057 TC3 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0058 TC4 hi Read Bit 15 14 13 12 1...

Page 37: ...ite 006D TIMTST Test Only Read 0 0 0 0 0 0 TCBYP 0 Write 006E Reserved Read Write 006F Reserved Read Write 0070 PBCTL Read 0 PBEN 0 0 0 0 PBOVI 0 Write 0071 PBFLG Read 0 0 0 0 0 0 PBOVF 0 Write 0072 P...

Page 38: ...0084 ATD0CTL4 Read SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Write 0085 ATD0CTL5 Read DJM DSGN SCAN MULT 0 CC CB CA Write 0086 ATD0STAT0 Read SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 Write 0087 Reserved Read 0...

Page 39: ...D0DR7H Read Bit15 14 13 12 11 10 9 Bit8 Write 009F ATD0DR7L Read Bit7 Bit6 0 0 0 0 0 0 Write 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Page 40: ...0 0 0 0 00B3 PWMCNT7 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00B4 PWMPER0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00B5 PWMPER1 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00B6 PWMPER2 Read Bit 7 6 5 4 3...

Page 41: ...SWAI RSRC M WAKE ILT PE PT Write 00CB SCI0CR2 Read TIE TCIE RIE ILIE TE RE RWU SBK Write 00CC SCI0SR1 Read TDRE TC RDRF IDLE OR NF FE PF Write 00CD SCI0SR2 Read 0 0 0 0 0 BRK13 TXDIR RAF Write 00CE SC...

Page 42: ...00DC Reserved Read 0 0 0 0 0 0 0 0 Write 00DD SPI0DR Read Bit7 6 5 4 3 2 1 Bit0 Write 00DE Reserved Read 0 0 0 0 0 0 0 0 Write 00DF Reserved Read 0 0 0 0 0 0 0 0 Write 00E0 00E7 IIC Inter IC Bus Addr...

Page 43: ...ead 0 0 0 BDLCE 0 0 0 0 Write 00EF DLCBSTAT Read 0 0 0 0 0 0 0 IDLE Write 00F0 00F7 SPI1 Serial Peripheral Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00F0 SPI1CR1 Read SPIE...

Page 44: ...te 0108 FADDRHI Read 0 Bit 14 13 12 11 10 9 Bit 8 Write 0109 FADDRLO Read Bit 7 6 5 4 3 2 1 Bit 0 Write 010A FDATAHI Read Bit 15 14 13 12 11 10 9 Bit 8 Write 010B FDATALO Read Bit 7 6 5 4 3 2 1 Bit 0...

Page 45: ...FFC AWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF Write 0123 ATD1CTL3 Read 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 Write 0124 ATD1CTL4 Read SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 Write 0125 ATD1CTL5 Read DJM DSGN...

Page 46: ...013C ATD1DR6H Read Bit15 14 13 12 11 10 9 Bit8 Write 013D ATD1DR6L Read Bit7 Bit6 0 0 0 0 0 0 Write 013E ATD1DR7H Read Bit15 14 13 12 11 10 9 Bit8 Write 013F ATD1DR7L Read Bit7 Bit6 0 0 0 0 0 0 Write...

Page 47: ...AR4 CAN0IDAR7 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 015C 015F CAN0IDMR4 CAN0IDMR7 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0160 016F CAN0RXFG Read FOREGROUND RECEIVE BUFFER see Table 1 2 Write...

Page 48: ...xx14 xx1B CANxTDSR0 CANxTDSR7 Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write xx1C CANxTDLR Read DLC3 DLC2 DLC1 DLC0 Write xx1D CONxTTBPR Read PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 Write xx1E CAN...

Page 49: ...Read TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write 0190 0193 CAN1IDAR0 CAN1IDAR3 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 0194 0197 CAN1IDMR0 CAN1IDMR3 Read AM7 AM6 AM5 AM4 AM3 AM2...

Page 50: ...4A DDRS Read DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 Write 024B RDRS Read RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 Write 024C PERS Read PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W...

Page 51: ...2 DDRH1 DDRH0 Write 0263 RDRH Read RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 Write 0264 PERH Read PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 Write 0265 PPSH Read PPSH7 PPSH6 PPSH5 PPSH4 PPS...

Page 52: ...XEIE0 Write 0288 CAN4TARQ Read 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 Write 0289 CAN4TAAK Read 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 Write 028A CAN4TBSEL Read 0 0 0 0 0 TX2 TX1 TX0 Write 028B CAN4IDAC Read 0 0 IDAM1...

Page 53: ...NNIF SLMMIF 0 XSYNIF OPTDF Write 0307 BFGISR Read TXIF OVRNIF ERRIF SYNEIF SYNLIF ILLPIF LOCKIF WAKEIF Write 0308 BFRIER Read RCVFIE RXIE SYNAIE SYNNIE SLMMIE 0 XSYNIE 0 Write 0309 BFGIER Read TXIE OV...

Page 54: ...D7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Write 0321 BFTLEN Read LEN3 LEN2 LEN1 LEN0 Write 0322 032D BFTDATA0 BFTDATA11 Read DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Write 032E 032F Reserved Read Write 03...

Page 55: ...2 Module Mapping Control MMC Block Guide for further details 0360 03FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0360 03FF Reserved Read 0 0 0 0 0 0 0 0 Write Table 1 3 Ass...

Page 56: ...Device User Guide 9S12DT128DGV2 D V02 16 56 Freescale Semiconductor...

Page 57: ...ignals It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S12DT128 and its derivatives are available in a 112...

Page 58: ...C2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC TAGHI BKGD ADDR0 DATA0 PB0 ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4...

Page 59: ...ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PA0 ADDR8 DATA8 PP4 KWP4 PWM4 PP5 KWP5 PWM5 PP7 KWP7 PWM7 VDDX VSSX PM0 RXCAN0 RXB PM1 TXCAN0 TXB PM2 RXCAN1 RXCAN0...

Page 60: ...8 SC515846 SC102202 80 QFP VRH VDDA PAD07 AN07 ETRIG0 PAD06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02 PAD01 AN01 PAD00 AN00 VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PA5 ADDR13 DATA13 PA4 A...

Page 61: ...Inputs ATD1 PAD 7 AN0 7 ETRIG0 VDDA None None Port AD Input Analog Inputs External Trigger Input ATD0 PAD 6 0 AN0 6 0 VDDA None None Port AD Input Analog Inputs ATD0 PA 7 0 ADDR 15 8 DATA 15 8 VDDR PU...

Page 62: ...ts PK7 ECS ROMCTL VDDX PUCR PUPKE Up Port K I O Emulation Chip Select ROM Control PK 5 0 XADDR 19 14 VDDX PUCR PUPKE Up Port K I O Extended Addresses PM7 BF_PSLM TXCAN4 VDDX PERM PPSM Disabled Port M...

Page 63: ...1 MOSI1 VDDX PERP PPSP Disabled Port P I O Interrupt Channel 1 of PWM MOSI of SPI1 PP0 KWP0 PWM0 MISO1 VDDX PERP PPSP Disabled Port P I O Interrupt Channel 0 of PWM MISO2 of SPI1 PS7 SS0 VDDX PERS PPS...

Page 64: ...XFC PLL Loop Filter Pin PLL loop filter Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoide...

Page 65: ...ultiplexed external address and data bus 2 3 11 PB 7 0 ADDR 7 0 DATA 7 0 Port B I O Pins PB7 PB0 are general purpose input or output pins In MCU expanded modes of operation these pins are used for the...

Page 66: ...ator C1 CDC Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal bias conditions and recommended capacitor value CDC Please contact the crystal manu...

Page 67: ...2 3 16 PE3 LSTRB TAGLO Port E I O Pin 3 PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus a...

Page 68: ...enerate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 SPI1 2 3 26 PH1 KWH1 MOSI1 Port H I O Pin 1 PH1 is a ge...

Page 69: ...refer to 4 2 Chip Configuration Summary 2 3 32 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 PK5 PK0 are general purpose input or output pins In MCU expanded modes of operation these pins provide the expande...

Page 70: ...F of Byteflight It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 1 or 0 CAN1 or CAN0 It can be configured as the master input during master mo...

Page 71: ...be configured as Pulse Width Modulator PWM channel 2 output It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 SPI1 2 3 47 PP1 KWP1 PWM1 MOSI1 Port P I O Pin 1 PP1 is a...

Page 72: ...urpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 1 SCI1 2 3 55 PS1 TXD0 Port S I O Pin 1 PS1 is a general purpose input or output pin It can be...

Page 73: ...ecause fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Th...

Page 74: ...D Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground...

Page 75: ...signals for the core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide for details on clock generation Figure 3 1 Clock Co...

Page 76: ...Device User Guide 9S12DT128DGV2 D V02 16 76 Freescale Semiconductor...

Page 77: ...le in the memory map ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal For furth...

Page 78: ...user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through rese...

Page 79: ...ntroller features three main low power modes Consult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about t...

Page 80: ...Device User Guide 9S12DT128DGV2 D V02 16 80 Freescale Semiconductor...

Page 81: ...t CRGINT RTIE F0 FFEE FFEF Enhanced Capture Timer channel 0 I Bit TIE C0I EE FFEC FFED Enhanced Capture Timer channel 1 I Bit TIE C1I EC FFEA FFEB Enhanced Capture Timer channel 2 I Bit TIE C2I EA FFE...

Page 82: ...CNFG CCIE CBEIE BA FFB8 FFB9 FLASH I Bit FCNFG CCIE CBEIE B8 FFB6 FFB7 CAN0 wake up I Bit CANRIER WUPIE B6 FFB4 FFB5 CAN0 errors I Bit CANRIER CSCIE OVRIE B4 FFB2 FFB3 CAN0 receive I Bit CANRIER RXFIE...

Page 83: ...non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations...

Page 84: ...Device User Guide 9S12DT128DGV2 D V02 16 84 Freescale Semiconductor...

Page 85: ...trol MMC Block Description Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module 6 2 1 Device specific information INITEE Reset state 01 Bits EE11 EE15 are Write once...

Page 86: ...12 Breakpoint BKP Block Description Consult the BKP Block Guide for information on the HCS12 Breakpoint module Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guid...

Page 87: ...ck Description Consult the IIC Block User Guide for information about the Inter IC Bus module Section 12 Serial Communications Interface SCI Block Description There are two Serial Communications Inter...

Page 88: ...lash module Section 18 EEPROM 2K Block Description Consult the EETS2K Block User Guide for information about the EEPROM module Section 19 RAM Block Description This module supports single cycle misali...

Page 89: ...board area for C7 C8 C11 and Q1 as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU Central power input should b...

Page 90: ...T128DGV2 D V02 16 90 Freescale Semiconductor Figure 23 1 Recommended PCB Layout for 112LQFP Colpitts Oscillator C5 C4 C1 C6 C3 C2 C8 C7 Q1 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDD2 VSS2 VDDPLL VSSP...

Page 91: ...mmended PCB Layout for 80QFP MC9S12DG128E MC9S12DG128 MC9S12DJ128E MC9S12DJ128 MC9S12A128 SC515847 SC515848 SC101161DG SC101161DJ SC102203 and SC102204 Colpitts Oscillator C5 C4 C3 C2 C8 C7 C10 C9 R1...

Page 92: ...T128DGV2 D V02 16 92 Freescale Semiconductor Figure 23 3 Recommended PCB Layout for 112LQFP Pierce Oscillator C5 C4 C1 C6 C3 C2 C10 C9 R1 VDDX VSSX VDDR VSSR VDD1 VSS1 VDD2 VSS2 VDDPLL VSSPLL VDDA VSS...

Page 93: ...nded PCB Layout for 80QFP MC9S12DG128E MC9S12DG128 MC9S12DJ128E MC9S12DJ128 MC9S12A128 SC515847 SC515848 SC101161DG SC101161DJ SC102203 and SC102204 Pierce Oscillator C5 C4 C3 C2 C10 C9 R1 C6 C1 VDD1...

Page 94: ...Freescale Semiconductor Figure 23 5 Recommended PCB Layout for 80QFP MC9S12DB128 SC515846 and SC102202 Pierce Oscillator C5 C4 C3 C2 C10 C9 R1 C6 C1 VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL VDDA V...

Page 95: ...Device User Guide 9S12DT128DGV2 D V02 16 95 Freescale Semiconductor...

Page 96: ...Device User Guide 9S12DT128DGV2 D V02 16 96 Freescale Semiconductor...

Page 97: ...cross process variations They are regularly verified by production monitors T Those parameters are achieved by design characterization on a small sample size from typical devices All values shown in t...

Page 98: ...drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This class is made up by the two VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the...

Page 99: ...TES 1 Beyond absolute maximum ratings device might be damaged Num Rating Symbol Min Max Unit 1 I O Regulator and Analog Supply Voltage VDD5 0 3 6 0 V 2 Digital Logic Supply Voltage 2 2 The device cont...

Page 100: ...ce C V M with regards to the ambient temperature TA and the junction temperature TJ For power dissipation Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Human Body Seri...

Page 101: ...e device is powered from an external source VDD 2 35 2 5 2 75 V PLL Supply Voltage 1 VDDPLL 2 25 2 5 2 75 V Voltage Difference VDDX to VDDR and VDDA VDDX 0 1 0 0 1 V Voltage Difference VSSX to VSSR an...

Page 102: ...ed IDDR is the current shown in Table A 7 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high Which is the sum of all...

Page 103: ...sistance LQFP112 single sided PCB2 2 PC Board according to EIA JEDEC Standard 51 3 JA 54 o C W 2 T Thermal Resistance LQFP112 double sided PCB with 2 internal planes3 3 PC Board according to EIA JEDEC...

Page 104: ...age pins in output mode Partial Drive IOH 2 0mA Full Drive IOH 10 0mA V OH VDD5 0 8 V 6 C P Output Low Voltage pins in output mode Partial Drive IOL 2 0mA Full Drive IOL 10 0mA V OL 0 8 V 7 P Internal...

Page 105: ...ents and add the currents due to the external loads Table A 7 Supply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Run suppl...

Page 106: ...Device User Guide 9S12DT128DGV2 D V02 16 106 Freescale Semiconductor NOTES 1 PLL off Oscillator in Colpitts Mode 2 At those low power dissipation levels TJ TA can be assumed...

Page 107: ...nction with the source resistance there will be a voltage drop from the signal source to the ATD input The maximum source resistance RS Conditions are shown in Table A 4 unless otherwise noted Num C R...

Page 108: ...analog inputs greater than VRH and 000 for values less than VRL unless the current is higher than specified as disruptive conditions 2 Current is injected into pins in the neighborhood of the channel...

Page 109: ...in Table A 4 unless otherwise noted VREF VRH VRL 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV fATDCLK 2 0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10 Bit Resolution LSB 5 mV 2...

Page 110: ...o Table A 10 1 5 Vin mV 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 B...

Page 111: ...IV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as fNVMOP The minimum program and erase times shown in Table A 11 are calculated for maximum f...

Page 112: ...amming Time tswpgm 46 2 2 Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus 74 5 3 3 Maximum Erase and Programming times are achieved u...

Page 113: ...anteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program erase cycling are specified at the opera...

Page 114: ...refer to Engineering Bulletin EB618 Years 2 C Data retention with 100 program erase cycles at an average junction temperature TJavg 85 C 20 1002 3 C Number of program erase cycles 40 C TJ 0 C nFL 10...

Page 115: ...GV2 D V02 16 115 Freescale Semiconductor Figure A 2 Typical Endurance vs Temperature Typical Endurance 10 3 Cycles Operating Temperature TJ C 0 50 100 150 200 250 300 350 400 450 500 40 20 0 20 40 60...

Page 116: ...Device User Guide 9S12DT128DGV2 D V02 16 116 Freescale Semiconductor...

Page 117: ...n chip voltage regulator is intended to supply the internal logic and oscillator circuits No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Ty...

Page 118: ...Device User Guide 9S12DT128DGV2 D V02 16 118 Freescale Semiconductor...

Page 119: ...a Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDD5 is out of specification limits the SRAM contents integrity is guarantee...

Page 120: ...itts oscillator or Pierce oscillator external clock depends on the XCLKS signal which is sampled during reset By asserting the XCLKS input during reset this oscillator can be bypassed allowing the inp...

Page 121: ...fOSC 0 5 40 MHz 2 P Startup Current iOSC 100 A 3 C Oscillator start up time Colpitts tUPOSC 82 2 fosc 4MHz C 22pF 1003 3 Maximum value is for extreme cases using high Q low frequency crystals ms 4 D...

Page 122: ...C 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by The phase detector relationship is given by ich is the current in tracking mode The loop bandwidth fC should b...

Page 123: ...hown in Figure A 3 With each transition of the clock fcmp the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuous...

Page 124: ...imum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as For N 100 the following equation is a good fit for the maximum jitter Figure A 5 Maximu...

Page 125: ...on from target frequency 4 D Lock Detection Lock 0 1 5 1 5 D Un Lock Detection unl 0 5 2 5 1 6 D Lock Detector transition from Tracking to Acquisition mode unt 6 8 1 7 C PLLON Total Stabilization dela...

Page 126: ...Device User Guide 9S12DT128DGV2 D V02 16 126 Freescale Semiconductor...

Page 127: ...conductor A 6 MSCAN Table A 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN Wake up dominant pulse filter...

Page 128: ...Device User Guide 9S12DT128DGV2 D V02 16 128 Freescale Semiconductor...

Page 129: ...ate the master mode timing Timing values are shown in Table A 18 Figure A 6 SPI Master Timing CPHA 0 SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT SS1 OUTPUT 1 9 5 6 MSB IN2 BIT 6 1 LSB IN MSB OUT2 LSB...

Page 130: ...1 2 fbus 1 P SCK Period tsck 1 fop tsck 4 2048 tbus 2 D Enable Lead Time tlead 1 2 tsck 3 D Enable Lag Time tlag 1 2 tsck 4 D Clock SCK High or Low Time twsck tbus 30 1024 tbus ns 5 D Data Setup Time...

Page 131: ...re A 8 SPI Slave Timing CPHA 0 Figure A 9 SPI Slave Timing CPHA 1 SCK INPUT SCK INPUT MOSI INPUT MISO OUTPUT SS INPUT 1 9 5 6 MSB IN BIT 6 1 LSB IN MSB OUT SLAVE LSB OUT BIT 6 1 10 4 4 2 7 CPOL 0 CPOL...

Page 132: ...4 fbus 1 P SCK Period tsck 1 fop tsck 4 2048 tbus 2 D Enable Lead Time tlead 1 tcyc 3 D Enable Lag Time tlag 1 tcyc 4 D Clock SCK High or Low Time twsck tcyc 30 ns 5 D Data Setup Time Inputs tsu 25 n...

Page 133: ...ual timing values shown on table Table A 20 All major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bu...

Page 134: ...External Bus Timing Addr Data read Addr Data write addr data data 5 10 11 8 16 6 ECLK 1 2 3 4 addr data data 12 15 9 7 14 13 ECS 21 20 22 23 Non Multiplexed 17 19 LSTRB 29 NOACC 32 PIPO0 PIPO1 PE6 5...

Page 135: ...13 D Write data hold time tDHW 2 ns 14 D Write data setup time 1 PWEH tDDW tDSW 12 ns 15 D Address access time 1 tcyc tAD tDSR tACCA 19 ns 16 D E high access time 1 PWEH tDSR tACCE 6 ns 17 D Non multi...

Page 136: ...L tP0D tP0V 11 ns 35 D IPIPO 1 0 delay time 1 PWEH tP1V tP1D 2 25 ns 36 D IPIPO 1 0 valid time to E fall tP1V 11 ns NOTES 1 Affected by clock stretch add N x tcyc where N 0 1 2 or 3 depending on the n...

Page 137: ...Device User Guide 9S12DT128DGV2 D V02 16 137 Freescale Semiconductor Appendix B Package Information B 1 General This section provides the physical dimensions of the MC9S12DT128 packages...

Page 138: ...85 84 28 57 29 56 B V V1 B1 A1 S1 A S VIEW AB 0 10 3 C C2 2 0 050 SEATING PLANE GAGE PLANE 1 VIEW AB C1 Z Y E K R2 R1 0 25 J1 VIEW Y J1 P G 108X 4X SECTION J1 J1 BASE ROTATED 90 COUNTERCLOCKWISE METAL...

Page 139: ...ATCH AND ARE DETERMINED AT DATUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAM...

Page 140: ...Device User Guide 9S12DT128DGV2 D V02 16 140 Freescale Semiconductor...

Page 141: ...Device User Guide 9S12DT128DGV2 D V02 16 141 Freescale Semiconductor User Guide End Sheet...

Page 142: ...ypical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating p...

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