Freescale Semiconductor MC9S08PT60, Reference Manual

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The mode fault flag is cleared automatically by a read of the SPI Status Register (with
MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is
cleared, the SPI becomes a normal master or slave again.
16.4.8 Low Power Mode Options
This section describes the low power mode options.
16.4.8.1 SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the
SPI system is in a low-power, disabled state. SPI registers can still be accessed, but
clocks to the core of this module are disabled .
16.4.8.2 SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control
Register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode.
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power
conservation state when the CPU is in wait mode.
• If SPISWAI is set and the SPI is configured for master, any transmission and
reception in progress stops at wait mode entry. The transmission and reception
resumes when the SPI exits wait mode.
• If SPISWAI is set and the SPI is configured as a slave, any transmission and
reception in progress continues if the SPSCK continues to be driven from the
master. This keeps the slave synchronized to the master and the SPSCK.
If the master transmits data while the slave is in wait mode, the slave continues
to send data consistent with the operation mode at the start of wait mode (that is,
if the slave is currently sending its SPIx_D to the master, it continues to send the
same byte. Otherwise, if the slave is currently sending the last data received byte
from the master, it continues to send each previously received data from the
master byte).
Functional Description
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
462 Freescale Semiconductor, Inc.