Freescale Semiconductor KITVR500EVM, User Manual

Page: 18 / 27

Schematic
KTVR500UG Rev. 1.0 8/2014
18 Freescale Semiconductor, Inc.
Figure 14. KITVR500EVM LDO/Control Schematic Part 3
VR500 - CONTROL/I2C SIGNALS HEADER
STBY EN
INT_B
POR_B
VCCI2C
MCU_SCL
MCU_SDA
PVIN
SW VIN
VCCI2C
PVIN SWVIN
3 Y B T S
EN 3,5
INT_B 3
POR_B 3
MCU_SCL 3,5
MCU_SDA 3,5
J33
CON_2X10
1 2
3 4
6
5
7
8
9 10
11 12
13 14
15 16
17 18
19 20
REFOUT= DDR memory reference
voltage,10 mA.
V_LDO1= 0.80 to 1.55 V, 250 mA
V_LDO2 = 1.8 to 3.3 V, 100 mA
V_LDO4 = 1.8 to 3.3 V, 100 mA
V_LDO5 = 1.8 to 3.3 V, 200 mA
V_LDO3 = 1.8 to 3.3 V, 350 mA
VR500 - LDO & REFOUT O/P
TERMINAL BLOCK SECTION
GND
V_LDO1
REFOUT
GND
V_LDO3
V_LDO2
GND
V_LDO4
V_LDO5
V_LDO1 REFOUT
V_LDO5 V_LDO4
V_LDO3 V_LDO2
J27
SUB_TB_3X1
1
2
3
J18
SUB_TB_3X1
1
2
3
J21
SUB_TB_3X1
1
2
3
GND GND GND GND GND GND
GROUND TEST POINTS
TP31
DNP
TP42
DNP
TP28
DNP
TP2
DNP
TP1
DNP
TP41
DNP
MOUNTING HOLES
BH4
MTG
BH2
MTG
BH1
MTG
BH3
MTG