Freescale Semiconductor HCS08 Series, Reference Manual

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 237
TPM counter is a free-running counter then the update is made when the TPM counter changes
from 0xFFFE to 0xFFFF.
14.6.2.4 Center-Aligned PWM Mode
This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output
compare value in TPMCnVH:TPMCnVL determines the pulse width (duty cycle) of the PWM signal
while the period is determined by the value in TPMMODH:TPMMODL. TPMMODH:TPMMODL
should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous
results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMCnVH:TPMCnVL)
period = 2 x (TPMMODH:TPMMODL); TPMMODH:TPMMODL=0x0001-0x7FFF
If the channel-value register TPMCnVH:TPMCnVL is zero or negative (bit 15 set), the duty cycle will be
0%. If TPMCnVH:TPMCnVL is a positive value (bit 15 clear) and is greater than the (non-zero) modulus
setting, the duty cycle will be 100% because the duty cycle compare will never occur. This implies the
usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if you do not need
to generate 100% duty cycle). This is not a significant limitation. The resulting period would be much
longer than required for normal applications.
TPMMODH:TPMMODL=0x0000 is a special case that should not be used with center-aligned PWM
mode. When CPWMS=0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,
but when CPWMS=1 the counter needs a valid match to the modulus register somewhere other than at
0x0000 in order to change directions from up-counting to down-counting.
The output compare value in the TPM channel registers (times 2) determines the pulse width (duty cycle)
of the CPWM signal (
Figure 14-16 ). If ELSnA=0, a compare occurred while counting up forces the
CPWM output signal low and a compare occurred while counting down forces the output high. The
counter counts up until it reaches the modulo setting in TPMMODH:TPMMODL, then counts down until
it reaches zero. This sets the period equal to two times TPMMODH:TPMMODL.
Figure 14-16. CPWM Period and Pulse Width (ELSnA=0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
PERIOD
PULSE WIDTH
COUNT=
COUNT= 0
COUNT=
OUTPUT
COMPARE
(COUNT DOWN)
OUTPUT
COMPARE
(COUNT UP)
TPMCHn
2 x TPMMODH:TPMMODL
2 x TPMCnVH:TPMCnVL
TPMMODH:TPMMODL TPMMODH:TPMMODL