Freescale Semiconductor Energy Efficient Solutions Xtrinsic MMA8452Q Data Sheet: Technical Data Download Page 38

MMA8452Q

Sensors

38

Freescale Semiconductor, Inc.

0x2B: CTRL_REG2 System Control 2 Register

ST 

bit activates the self-test function. When ST is set, X, Y, and Z outputs will shift. 

RST

 bit is used to activate the software reset. 

The reset mechanism can be enabled in STANDBY and ACTIVE mode.

When the reset bit is enabled, all registers are rest and are loaded with default values. Writing ‘1’ to the RST bit immediately 

resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode. 

The I

2

C communication system is reset to avoid accidental corrupted data access.

At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero.

The 

(S)MODS[1:0] 

bits select which Oversampling mode is to be used shown in 

Table 58

. The Oversampling modes are 

available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0].

 

0x2B: CTRL_REG2 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ST

RST

0

SMODS1

SMODS0

SLPE

MODS1

MODS0

Table 57. CTRL_REG2 Description

ST

Self-Test Enable. Default value: 0.

0: Self-Test disabled; 1: Self-Test enabled

RST

Software Reset. Default value: 0.

0: Device reset disabled; 1: Device reset enabled.

SMODS[1:0]

SLEEP mode power scheme selection. Default value: 00.

See 

Table 58

 and 

Table 59

SLPE

Auto-SLEEP enable. Default value: 0.

0: Auto-SLEEP is not enabled;

1: Auto-SLEEP is enabled. 

MODS[1:0]

ACTIVE mode power scheme selection. Default value: 00.

See 

Table 58

 and 

Table 59

Table 58. MODS Oversampling Modes

(S)MODS1

(S)MODS0

Power Mode

0

0

Normal 

0

1

Low Noise Low Power

1

0

High Resolution

1

1

Low Power

Table 59. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR

Mode

Normal (00)

Low Noise Low Power (01)

High Resolution (10)

Low Power (11)

ODR

Current 

μ

A

OS Ratio

Current 

μ

A

OS Ratio

Current 

μ

A

OS Ratio

Current 

μ

A

OS  Ratio

1.56 Hz

24

128

8

32

165

1024

6

16

6.25 Hz

24

32

8

8

165

256

6

4

12.5 Hz

24

16

8

4

165

128

6

2

50 Hz

24

4

24

4

165

32

14

2

100 Hz

44

4

44

4

165

16

24

2

200 Hz

85

4

85

4

165

8

44

2

400 Hz

165

4

165

4

165

4

85

2

800 Hz

165

2

165

2

165

2

165

2

Summary of Contents for Energy Efficient Solutions Xtrinsic MMA8452Q

Page 1: ...nterface Two programmable interrupt pins for six interrupt sources Three embedded channels of motion detection Freefall or Motion Detection 1 channel Pulse Detection 1 channel Transient Detection 1 ch...

Page 2: ...MOD 10 5 Functionality 11 5 1 Device Calibration 12 5 2 8 bit or 12 bit Data 12 5 3 Low Power Modes vs High Resolution Modes 12 5 4 Auto WAKE SLEEP Mode 12 5 5 Freefall and Motion Detection 12 5 6 Tra...

Page 3: ...ction i e fast motion transient Orientation with Set Hysteresis and Z lockout Shake Detection through Motion Threshold Auto WAKE Auto SLEEP Configurable with debounce counter and multiple motion inter...

Page 4: ...are described in detail in the register setting section Figure 3 Landscape Portrait Orientation Figure 4 Application Diagram Top View PU Earth Gravity Pin 1 Xout 0g Yout 1g Zout 0g Xout 1g Yout 0g Zo...

Page 5: ...refore require a pullup resistor as shown in the application diagram in Figure 4 1 1 Soldering Information The QFN package is compliant with the RoHS standard Please refer to AN4077 Table 1 Pin Descri...

Page 6: ...ehavior is also seen when changing from 800 Hz to any other data rate in the Normal Low Noise Low Power or High Resolution mode Soa 2 64 Sensitivity Change vs Temperature FS 1 0 set to 00 2g Mode TCSo...

Page 7: ...ass Cap VDD 2 5V Idd Boot 1 mA Value of Capacitor on BYP Pin 40 C 85 C Cap 75 100 470 nF STANDBY Mode Current 25 C VDD 2 5V VDDIO 1 8V STANDBY Mode IddStby 1 8 5 A Digital High Level Input Voltage SCL...

Page 8: ...t stretch the LOW period tLOW of the SCL signal s SDA setup time tSU DAT 100 ns SCL clock low time tLOW 1 3 s SCL clock high time tHIGH 0 6 s SDA and SCL rise time tr 20 0 1 Cb 3 3 Cb total capacitanc...

Page 9: ...osing it to extensive mechanical stress 3 3 Self Test Self T est checks the transducer functionality without external mechanical stimulus When Self T est is activated an electrostatic actuation force...

Page 10: ...ction of this document Table 7 Mode of Operation Description Mode I2 C Bus State VDD Function Description OFF Powered Down 1 8 V VDDIO Can be VDD The device is powered off All analog and digital block...

Page 11: ...ith directional information 1 channel Portrait Landscape detection with trip points fixed at 30 and 60 for smooth transitions between orientations All functionality is available in 2g 4g or 8g dynamic...

Page 12: ...at 1 56 Hz There is a trade off between low power and high resolution Low Power can be achieved when the oversampling rate is reduced The lowest power is achieved when MODS 11 or when the sample rate...

Page 13: ...ere high frequency data is considered noise However there are many functions where the accelerometer must analyze dynamic acceleration Functions such as tap flick shake and step counting are based on...

Page 14: ...ve for orientation detection as low as 29 from flat Figure 9 Illustration of Z Tilt Angle Lockout Transition Top View PU Earth Gravity Pin 1 Xout 0g Yout 1g Zout 0g Xout 1g Yout 0g Zout 0g Xout 0g You...

Page 15: ...ctions of the device for Motion Freefall Transient Orientation and Pulse The registers embedded inside the MMA8452Q are accessed through the I2C serial interface Table 9 To enable the I2C interface VD...

Page 16: ...mand begins on the falling edge of SCL After the eight clock cycles are used to send the command note that the data returned is sent with the MSB first once the data is received Figure 11 shows the ti...

Page 17: ...0x39 Write 001110 0 0x1C 0 0x38 Read 001110 1 0x1D 1 0x3B Write 001110 1 0x1D 0 0x3A Single Byte Read Master ST Device Address 6 0 W Register Address 7 0 SR Device Address 6 0 R NAK SP Slave AK AK AK...

Page 18: ...x80 Landscape Portrait configuration PL_COUNT 3 4 R 0x12 0x13 00000000 0x00 Landscape Portrait debounce counter PL_BF_ZCOMP 3 4 R 0x13 0x14 01000100 0x44 Back Front Z Lock Trip threshold P_L_THS_REG 3...

Page 19: ...mode occurs 2 This register data is only valid in ACTIVE mode 3 Register contents are preserved when transition from ACTIVE to STANDBY mode occurs 4 Modification of this register s contents can only...

Page 20: ...0x06 OUT_Z_LSB These registers contain the X axis Y axis and Z axis 12 bit output sample data expressed as 2 s complement numbers The sample data output registers store the current sample data OUT_X_...

Page 21: ...SRC_TRANS Transient interrupt status bit Default value 0 Logic 1 indicates that an acceleration transient value greater than user specified threshold has occurred Logic 0 indicates that no transient e...

Page 22: ...lementation on the high pass filter refer to Freescale application note AN4071 0x0D WHO_AM_I Device ID Register Read Only Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 0 1 0 1 0 0x0E XYZ_DATA_...

Page 23: ...0 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 0 5 Hz 0 5 Hz 0 5 Hz 0 1 8 Hz 8 Hz 4 Hz 2 Hz 1 Hz 0 25 Hz 0 25 Hz 0 25 Hz 1 0 4 Hz 4 Hz 2 Hz 1 Hz 0 5 Hz 0 125 Hz 0 125 Hz 0 125 Hz 1 1 2 Hz 2 Hz 1 Hz 0 5 Hz 0 25 Hz 0 06...

Page 24: ...de selection Default value 1 0 Decrements debounce whenever condition of interest is no longer valid 1 Clears counter whenever condition of interest is no longer valid PL_EN Portrait Landscape Detecti...

Page 25: ...nd or XEFE are set The event flags ZHE ZHP YHE YHP XHE and XHP are latched when the EA event bit is set The event flags ZHE ZHP YHE YHP XHE and XHP will start changing only after the FF_MT_SRC registe...

Page 26: ...on detection where the magnitude of the X or Y or Z acceleration value is higher than the threshold value Figure 12 FF_MT_CFG High and Low g Level 0x16 FF_MT_SRC Freefall Motion Source Register 0x15 F...

Page 27: ...longer true Figure 13 c until the debounce counter reaches 0 or the inertial event of interest becomes active Decrementing the debounce counter acts as a median enabling the system to filter out irre...

Page 28: ...ce sample count depends on the ODR chosen and the Oversampling mode as shown in Table 30 0x18 FF_MT_COUNT_Register Read Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 Ta...

Page 29: ...tion High g Event on Count Threshold FF FFEA all 3 axis Motion Detect Counter Value High g Event on Count Threshold Debounce a all 3 axis Motion Detect Counter Value High g Event on Count Threshold De...

Page 30: ...bled 1 Event flag latch enabled ZTEFE Event flag enable on Z transient acceleration greater than transient threshold event Default value 0 0 Event detection disabled 1 Raise event flag on measured acc...

Page 31: ...r of debounce counts continuously matching the condition where the unsigned value of high pass filtered data is greater than the user specified value of TRANSIENT_THS The time step for the transient d...

Page 32: ...vent flag latch enabled ZDPEFE Event flag enable on double pulse event on Z axis Default value 0 0 Event detection disabled 1 Event detection enabled ZSPEFE Event flag enable on single pulse event on...

Page 33: ...ailable are dependent on the Oversampling mode and whether the Pulse Low Pass Filter option is enabled or not The Pulse Low Pass Filter is set in Register 0x0F 0x23 PULSE_THSX Register Read Write Bit...

Page 34: ...1 0 159 10 2 5 20 0 625 40 0x27 PULSE_LTCY Register Read Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LTCY7 LTCY6 LTCY5 LTCY4 LTCY3 LTCY2 LTCY1 LTCY0 Table 44 PULSE_LTCY Description LTCY 7 0...

Page 35: ...IND0 Table 47 PULSE_WIND Description WIND 7 0 Second Pulse Time Window Default value 0000_0000 Table 48 Time Step for PULSE Detection Window ODR and Power Mode Reg 0x0F Pulse_LPF_EN 1 ODR Hz Max Time...

Page 36: ...can be enabled In order to WAKE the device four functions are provided Transient Orientation Pulse and the Motion Freefall The Auto WAKE SLEEP interrupt does not affect the WAKE SLEEP nor does the da...

Page 37: ...ted the auto increment counter will skip over the LSB data bytes 0x2A CTRL_REG1 Register Read Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTI...

Page 38: ...it 3 Bit 2 Bit 1 Bit 0 ST RST 0 SMODS1 SMODS0 SLPE MODS1 MODS0 Table 57 CTRL_REG2 Description ST Self Test Enable Default value 0 0 Self Test disabled 1 Self Test enabled RST Software Reset Default va...

Page 39: ...LSE 0 Pulse function is bypassed in SLEEP mode Default value 0 1 Pulse function interrupt can wake up system WAKE_FF_MT 0 Freefall Motion function is bypassed in SLEEP mode Default value 0 1 Freefall...

Page 40: ...ASLP 0 INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT 0 INT_CFG_DRDY Table 62 Interrupt Configuration Register Description Interrupt Configuration Description INT_CFG_ASLP INT1 INT2 Configur...

Page 41: ...ZHP YHE YHP XHE XHP 17 FF_MT_THS Freefall Motion Threshold R W DBCNTM THS6 THS5 THS4 THS3 THS2 THS1 THS0 18 FF_MT_COUNT Freefall Motion Debounce R W D7 D6 D5 D4 D3 D2 D1 D0 1D TRANSIENT_CFG Transient...

Page 42: ...4g 2 mg Range 8g 3 9 mg 0111 1111 1111 1 999g 3 998g 7 996g 0111 1111 1110 1 998g 3 996g 7 992g 0000 0000 0001 0 001g 0 002g 0 004g 0000 0000 0000 0 0000g 0 0000g 0 0000g 1111 1111 1111 0 001g 0 002g...

Page 43: ...over any of the PCB landing pads as shown in Figure 14 7 No additional via nor metal pattern underneath package on the top of the PCB layer 8 Do not place any components or vias within 2 mm of the pac...

Page 44: ...25 m The PCB should be rated for the multiple lead free reflow condition with a maximum 260 C temperature Use a standard pick and place process and equipment Do not use a hand soldering process Do not...

Page 45: ...formation The MMA8451Q device is housed in a 16 lead QFN package case number 2077 8 1 Product identification markings 8 2 Tape and reel information Top View 263 8451 ALYW Traceability date code Assemb...

Page 46: ...MMA8452Q Sensors 46 Freescale Semiconductor Inc 8 3 Package Description CASE 2077 02 ISSUE A 16 LEAD QFN...

Page 47: ...MMA8452Q Sensors Freescale Semiconductor Inc 47 PACKAGE DIMENSIONS CASE 2077 02 ISSUE A 16 LEAD QFN...

Page 48: ...MMA8452Q Sensors 48 Freescale Semiconductor Inc PACKAGE DIMENSIONS CASE 2077 02 ISSUE A 16 LEAD QFN...

Page 49: ...espectively 8 07 2013 Table 2 Updated Self test Output Change row X Y and Z Typ values from 181 255 and 1680 to 44 61 and 392 respectively 8 1 10 2013 Table 3 Updated Parameter and Test Condition colu...

Page 50: ...ims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale data sheets and or specifications can and do vary in dif...

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