MMA8452Q
Sensors
38
Freescale Semiconductor, Inc.
0x2B: CTRL_REG2 System Control 2 Register
ST
bit activates the self-test function. When ST is set, X, Y, and Z outputs will shift.
RST
bit is used to activate the software reset.
The reset mechanism can be enabled in STANDBY and ACTIVE mode.
When the reset bit is enabled, all registers are rest and are loaded with default values. Writing ‘1’ to the RST bit immediately
resets the device, no matter whether it is in ACTIVE/WAKE, ACTIVE/SLEEP, or STANDBY mode.
The I
2
C communication system is reset to avoid accidental corrupted data access.
At the end of the boot process the RST bit is deasserted to 0. Reading this bit will return a value of zero.
The
(S)MODS[1:0]
bits select which Oversampling mode is to be used shown in
. The Oversampling modes are
available in both WAKE Mode MOD[1:0] and also in the SLEEP Mode SMOD[1:0].
0x2B: CTRL_REG2 Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ST
RST
0
SMODS1
SMODS0
SLPE
MODS1
MODS0
Table 57. CTRL_REG2 Description
ST
Self-Test Enable. Default value: 0.
0: Self-Test disabled; 1: Self-Test enabled
RST
Software Reset. Default value: 0.
0: Device reset disabled; 1: Device reset enabled.
SMODS[1:0]
SLEEP mode power scheme selection. Default value: 00.
SLPE
Auto-SLEEP enable. Default value: 0.
0: Auto-SLEEP is not enabled;
1: Auto-SLEEP is enabled.
MODS[1:0]
ACTIVE mode power scheme selection. Default value: 00.
Table 58. MODS Oversampling Modes
(S)MODS1
(S)MODS0
Power Mode
0
0
Normal
0
1
Low Noise Low Power
1
0
High Resolution
1
1
Low Power
Table 59. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR
Mode
Normal (00)
Low Noise Low Power (01)
High Resolution (10)
Low Power (11)
ODR
Current
μ
A
OS Ratio
Current
μ
A
OS Ratio
Current
μ
A
OS Ratio
Current
μ
A
OS Ratio
1.56 Hz
24
128
8
32
165
1024
6
16
6.25 Hz
24
32
8
8
165
256
6
4
12.5 Hz
24
16
8
4
165
128
6
2
50 Hz
24
4
24
4
165
32
14
2
100 Hz
44
4
44
4
165
16
24
2
200 Hz
85
4
85
4
165
8
44
2
400 Hz
165
4
165
4
165
4
85
2
800 Hz
165
2
165
2
165
2
165
2