Debug Support
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
9-21
properly masked by debug firmware (interrupts, machine checks, bus error conditions, and so on) and may
prevent the desired instruction from being successfully executed. The OSR[ERR] bit is set to indicate this
condition. In these cases, values in the CPUSCR correspond to the first instruction of the exception
handler.
Additionally, while single-stepping, to prevent debug events from generating debug interrupts,
DBCR0[EDM] is internally forced to 1. Also, during a debug session, DBSR and DBCNT are frozen from
updates due to debug events regardless of DBCR0[EDM]. They may still be modified during a debug
session through a single-stepped mtspr instruction if DBCR0[EDM] is cleared, or through OnCE access
if DBCR0[EDM] is set.
9.5.5.3
OnCE Control Register (OCR)
The OCR, shown in
, forces the core into debug mode and enables/disables sections of the OnCE
control logic. It also provides control over the MMU during a debug session. (See
Cache Operation during Debug.”
) The control bits are read/write. These bits are effective only while OnCE
is enabled (jd_en_once set).
describes OnCE control register fields.
0
7
8
9 10
11
12
13
14
15
16
17 18
19
20
21
22
23 24
28
29
30
31
Field
—
I_DMDIS — I_DVLE I_DI I_DM I_DE DMDIS
—
DW DI DM DG DE
—
WKUP FDB DR
Reset
0x0000_0000 on
m_por, j_trst_b, or entering test-logic-reset state
Figure 9-7. OnCE Control Register
Table 9-8. OnCE Control Register Bit Definitions
Bits
Name
Description
0–7
—
Reserved, should be cleared.
8
I_DMDIS
Instruction side debug MMU disable control bit. May be used to control whether the MMU is enabled or
disabled during a debug session for instruction accesses.
0 MMU not disabled for debug sessions. The MMU functions normally.
1 MMU disabled for debug sessions. For instruction accesses, no address translation is performed (1:1
address mapping) and the TLB IME bits are taken from the OCR bits I_DI, I_DM, and I_DE. The SX and
UX access permission control bits are set, allowing full access. When disabled, no TLB miss or TLB
exceptions are generated for instruction accesses. External access errors can still occur.
9–10
—
Reserved, should be cleared.
11
I_DVLE
Instruction side debug TLB VLE attribute bit. Provides the VLE attribute bit for when the MMU is disabled
during a debug session.
12
I_DI
Instruction side debug TLB I attribute bit. Provides the I attribute bit for instruction accesses when the MMU
is disabled for instruction accesses during a debug session.
13
I_DM
Instruction side debug TLB M attribute bit. Provides the M attribute bit to be used for instruction accesses
when the MMU is disabled for instruction accesses during a debug session.
14
—
Reserved, should be cleared.
15
I_DE
Instruction side debug TLB E attribute bit. Provides the E attribute bit for instruction accesses when the MMU
is disabled for instruction accesses during a debug session.
