Pulse-Width Modulation (PWM) Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
24-5
24.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
The PWMPRCLK register selects the prescale clock source for clocks A and B independently. If the clock
prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during
the transition.
Table 24-4. PWMCLK Field Descriptions
Field
Description
7,5,3,1
PCLK
n
PWM channel
n
clock select. Selects between one of two clock sources for each PWM channel. See
“PWM Prescale Clock Select Register (PWMPRCLK)”
and
Section 24.2.7, “PWM Scale A Register (PWMSCLA)”
for
more information on how the different clock rates are generated. The even-numbered channels’ clock select has no
effect when the corresponding PWMCTL[CON
n(n+1)
] bit is set. For example, if PWMCTL[CON01] equals 1,
PWMCLK[PCLK0] has no affect.
6,4,2,0
Reserved, should be cleared.
IPSBAR
Offset:
0x1B_0003 (PWMPRCLK)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
0
PCKB
0
PCKA
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-5. PWM Prescale Clock Select Register (PWMPRCLK)
Table 24-5. PWMPRCLK Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–4
PCKB
Clock B prescaler select. These three bits control the rate of Clock B which can be used for PWM channels 3 and 7.
PCLK7
(PCLK7 Clock
Source)
PCLK5
(PWM5 Clock
Source)
PCLK3
(PWM3 Clock
Source)
PCLK1
(PWM1 Clock
Source)
0
B
A
B
A
1
SB
SA
SB
SA
PCKB Clock
B
Rate
000
Internal bus clock
÷
2
0
001
Internal bus clock
÷
2
1
...
...
111
Internal bus clock
÷
2
7
