Freescale Semiconductor ColdFire MCF5211, Reference Manual

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UART Modules
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
21-20 Freescale Semiconductor
programmed clock source. The lsb is received first. The data then transfers to a receiver holding register
and USR
n [RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the
receiver holding register are cleared.
After the stop bit is detected, receiver immediately looks for the next start bit. However, if a non-zero
character is received without a stop bit (framing error) and U
n RXD remains low for one-half of the bit
period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error,
framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error
and break flags in the USR
n at the received character boundary. They are valid only if USR n [RXRDY] is
set.
If a break condition is detected (U n RXD is low for the entire character including the stop bit), a character
of all 0s loads into the receiver holding register and USR n [RB,RXRDY] are set. U n RXD must return to a
high condition for at least one-half bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break persists through the
next character time. If the break begins in the middle of a character, receiver places the damaged character
in the Rx FIFO and sets the corresponding USR
n error bits and USR n [RXRDY]. Then, if the break lasts
until the next character time, receiver places an all-zero character into the Rx FIFO and sets
USR
n [RB,RXRDY].
Figure 21-20 shows receiver functional timing.
Figure 21-20. Receiver Timing Diagram
C1 C2 C4 C6 C7
C8
C3 C5
C6, C7, and C8 will be lost
(C2)
Status
Data
(C3)
Status
Data
(C4)
Status
Data
C5 will
be lost
Reset by
command
U n TXD
Receiver
Enabled
USR n [RXRDY]
Overrun
U n RTS
1
internal
module
select
USR n [FFULL]
(C1)
Status
Data
USR n [OE]
Automatically asserted
when ready to receive Manually asserted first time,
automatically negated if overrun occurs
UOP0[RTS] = 1
1
UMR2 n [TXRTS] = 1