Freescale Semiconductor ColdFire MCF5211, Reference Manual

Page: 224 / 544

DMA Controller Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
14-6 Freescale Semiconductor
14.3.4 Byte Count Registers (BCR n ) and DMA Status Registers (DSR n )
The Byte Count Registers (BCR n ) and DMA Status Registers (DSR n ) are two logical registers that occupy
one 32-bit register, as shown in Figure 14-6 . The address used to access both registers is the same; DSR n
occupies bits 31–24, and BCR n occupies bits 23–0.
BCR n contains the number of bytes yet to be transferred for a given block. BCR n decrements on the
successful completion of the address transfer of a write transfer. BCR n decrements by 1, 2, 4, or 16 for
byte, word, longword, or line accesses, respectively.
The fields of the DSR n register (bits 31–24 in Figure 14-6 ) are shown in Figure 14-7 . In response to an
event, the DMA controller writes to the appropriate DSR n bit. Only a write to DSR n [DONE] results in
action. DSR n [DONE] is set when the block transfer is complete.
When a transfer sequence is initiated and BCR n [BCR] is not a multiple of 16, 4, or 2 when the DMA is
configured for line, longword, or word transfers, respectively, DSR n [CE] is set and no transfer occurs.
IPSBAR
Offsets:
0x00_0104 (DAR0)
0x00_0114 (DAR1)
0x00_0124 (DAR2)
0x00_0134 (DAR3) Access: read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DAR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 14-5. Destination Address Registers (DAR n )
IPSBAR
Offsets:
0x00_0108 (BCR0/DSR0)
0x00_0118 (BCR1/DSR1)
0x00_0128 (BCR2/DSR2)
0x00_0138 (BCR3/DSR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DSR BCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 14-6. Byte Count Registers (BCR n ) and DMA Status Registers (DSR n )