Freescale Semiconductor 56F8300 Series, User Manual

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56F8357EVM User Manual, Rev. 1
2-18 Freescale Semiconductor
Preliminary
2.11.2 Memory Daughter Card Connector
The processor’s external memory bus signals are connected to the Memory Daughter Card
connector, J2.
Table 2-12 shows the port signal-to-pin assignments.
87 AN2 88 AN3
89 AN4 90 AN5
91 AN6 92 AN7
93 AN8 94 AN9
95 AN10 96 AN11
97 AN12 98 AN13
99 AN14 100 AN15
Table 2-12. Memory Daughter Card Connector Description
J2
Pin # Signal Pin # Signal
1 A4 / PA12 2 A5 / PA13
3 A3 / PA11 4 A6 / PE2
5 A2 / PA10 6 A7 / PE3
7 A 1/ PA9 8 RD
9 GND 10 GND
11 A0 / PA8 12 DS / CS1
13 PS / CS0 14 PD0 / CS2
15 D0 / PF9 16 D15 / PF8
17 D1 / PF10 18 D14 / PF7
19 GND 20 GND
21 GND 22 GND
23 D2 / PF11 24 D13 / PF6
25 D3 / PF12 26 D12 / PF5
Table 2-11. Peripheral Daughter Card Connector Description (Continued)
J1
Pin # Signal Pin # Signal