Chapter 3 BIOS Description
30
v
Upstream/Downstream LDT Bus Width
This option allows you to select upstream/downstream LDT(Lightning Data
Transport) bus width.
v
PCI Delay Transaction
This option allows you to enable or disable PCI delay transaction. The setting
value are: Disabled and Enabled.
v
PCI1/PCI2 Master 0 WS Write
This option is used to set the
PCI1/PCI2 Master 0 WS Write.
v
PCI1/PCI2 Post Write
This option is used to set the
PCI1/PCI2 Post Write.
v
LDT Bus Frequency
This option allows you to select LDT bus frequency.
LDT & PCI Bus Control Menu
v
Memory hole Remapping
This item is used to enable or disable the
Memory hole Remapping.
v
Bottom of UMA DRAM [31:24]
This item is used to set Bottom of UMA DRAM [31:24].
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