Force SPARC/CPCI-520G, Technical Reference Manual

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Ethernet and EBus2 Devices – PCIO Hardware Description
Page 80 SPARC/CPCI-52x(G)
Programming the
boot or user flash
EPROM Boot flash EPROM and user flash EPROM are on-board programmable
if the switch-selectable hardware write protection is disabled (see
section 4.4 “Switch Settings” on page 27).
Caution
Before programming the boot flash EPROM on-board, save the area
containing the OpenBoot image for reprogramming purposes. For
example, damage to the image in the boot flash EPROM can occur, if
power fails during on-board reprogramming.
To reprogram the boot flash EPROM, see also section 7.3.1 “Copying the
OpenBoot Image from Boot PROM to Boot Flash EPROM” on page 116.
6.3.4 Serial Interfaces – SAB 82532
The Base-520(G) provides 2 independent full-duplex serial I/O interfaces
(A and B). They are implemented via the Enhanced Serial Communica-
tion Controller – SAB 82532 User’s Manual and Addendum at PCI bus
base address
F140.000016
on the EBus2.
Device features • 2 independent full-duplex serial channels
• 2 independent baud rate generators
• Hardware handshake support
F000.0000
16
…F00F.FFFF
16
Default config. with SW6-2 = OFF in
case of 4-MByte user flash fact. opt. 1 MByte boot PROM
one 27C080, 1Mbx8
read-only device
F020.0000
16
…F05F.FFFF
16
4 MByte user flash EPROM
two 29F016, 2Mbx8, 5V
write-protectable via SW4-4
F060.0000
16
…F0FF.FFFF
16
10 MByte unused
F000.0000
16
…F01F.FFFF
16
Alternative config. with SW6-2 = ON
in case of 4-MByte user flash fact. opt. 2 MByte boot flash EPROM
one 29F016, 2Mbx8, 5V
write-protectable via SW4-3
F020.0000
16
…F05F.FFFF
16
4 MByte user flash EPROM
two 29F016, 2Mbx8, 5V
write-protectable via SW4-4
F060.0000
16
…F0FF.FFFF
16
10 MByte unused
Table 39 Boot and user flash address space configuration
PCI addr. range Configuration Device type