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Edge 2 – User Manual 

MIXTILE 

 
V1.1 

Copyright 

©

 2021 MIXTILE. 

 

1.4

 

Key Component Specifications 

The key component specifications are described below with relevant hardware information and 
developing notices. For more information, pin assignments and signal descriptions are listed in 
Chapter 2, Connectors & Pin Assignments. 

1.4.1

 

MIXTILE Core 3568 

The Core 3568 is a System-on-Module that expands all CPU functions to pins with an innovative 
connector. The Rockchip RK3568 ARM64 CPU contains many peripherals to support multi-purpose. 

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Quad Cortex-A55 processing cores 

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Core operating frequencies up to 2.0GHz 

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Neural Process Unit with processing performance up to 0.8 TOPS 

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Support 4k@60fps H.265/H.264/VP9 decoder; 1080P@100fps H.265/H.264 encoder 

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LPDDR4 SDRAM supports up to 8GB 

The SDRAM is 32bits data width, 4 ranks LPDDR4 memory capacities from 2GBytes to 8GBytes. 
The system flash memory supports eMMC 5.1 memory capacities from 16GBytes to 256GBytes. 
The default memory setting is 2/4GBytes LPDDR4 and 16/32GBytes eMMC for Edge 2. 

1.4.2

 

Wi-Fi 6 / Bluetooth 

Edge 2 integrates a Wi-Fi and Bluetooth module AP6275S, that can wake up the device from sleep 
mode. AP6275S supports Wi-Fi 6 and dual-mode Bluetooth 5.0 that could interact with different 
vendors’ 802.11a/b/g/n/ac/ax 2x2 Access Points with MIMO standard and can accomplish up to a 
speed of 1200Mbps with the dual stream. Wi-Fi wake and enable signals connect to 

GPIO0

 in the 

processor, which can be operating while the device is sleep. 

 

 

 

Summary of Contents for MIXTILE Edge 2

Page 1: ...IEC EDGE2 0432 Single Board Computer User Manual Get Started with https www mixtile com wiki...

Page 2: ...Quad core Cortex A55 SoC Processor RK3568 up to 2 0GHz l 2 4GBytes LPDDR4 SDRAM Memory l 16 32GBytes eMMC Flash Memory l 0 8 Tops NPU l Wi Fi 6 802 11ax l Dual Mode Bluetooth 5 0 l Support 4G 5G LoRa...

Page 3: ...rmance up to 0 8 TOPS l Support 4k 60fps H 265 H 264 VP9 decoder 1080P 100fps H 265 H 264 encoder l LPDDR4 SDRAM supports up to 8GB The SDRAM is 32bits data width 4 ranks LPDDR4 memory capacities from...

Page 4: ...M 2 socket supports one standard USB 3 0 interface Since the USB 3 0 data signals and one lane of PCIe data signals are using the same set of pins a GPIO is used to select USB 3 0 and a lane of two la...

Page 5: ...SB 2 0 3 0 port connects M 2 socket These USB 2 0 3 0 ports are provided by a USB 3 0 hub VL817 The three type A connectors support 5V at 1A power and dependent software power dis enabling 1 4 9 RS485...

Page 6: ...0 signal and another set of RGMII for ethernet 1 4 12 Buttons LEDs The POWER button controls three statuses of the device on off and sleep Short press POWER button to turn on device when the device is...

Page 7: ...ound 2 2 UART UART 3 Pin Pin Name Pin Type Input Output Signal Description 1 3 3V PWR Output 3 3V 100mA Max 2 UART3_RX IO Input UART3 serial data input 3 UART3_TX IO Output UART3 serial data output 4...

Page 8: ...al 2 5V PWR Output 5V 2A Max in total 3 GND GND Ground 4 GND GND Ground 2 6 Power button connector Pin Pin Name Pin Type Input Output Signal Description 1 PWRON_CON IO Input Active low same as PWR but...

Page 9: ...DC_VIN6 ANA Input ADC analog signal 5 SARADC_VIN7 ANA Input ADC analog signal 6 GND GND Ground 2 11 Speaker Pin Pin Name Pin Type Input Output Signal Description 1 SPK ANA Output speaker driver output...

Page 10: ...gnal Negative 15 MIPI_DSI_TX0_D3P LVDS Output MIPI DSI0 data signal Positive 16 GND GND Ground 17 LCD0_BL_PWM4 IO Output PWM Output for backlight adjust 18 NC Not connected pin 19 3 3V PWR Output 3 3V...

Page 11: ...ut for lcd reset 21 SARADC_VIN2_LCD_ID ANA Input Analog signal Input 22 LCD1_PWREN_H_GPIO4_D2 IO Output GPIO output for lcd power enable 23 I2C1_SCL_TP IO Output I2C clock signal for touch panel 24 I2...

Page 12: ...light 30 12V PWR Output 12V power supply for backlight 2 16 Camera Pin Pin Name Pin Type Input Output Signal Description 1 GND GND Ground 2 MIPI_CSI_RX_D0N LVDS Input MIPI_CSI data signal Negative 3 M...

Page 13: ...CLK1 IO Output CLOCK output for camera 37 GND GND Ground 38 MIPI_CSI_RX_CLK1N LVDS Input MIPI_CSI clock signal Negative 39 MIPI_CSI_RX_CLK1P LVDS Input MIPI_CSI clock signal Positive 40 GND GND Ground...

Page 14: ...n 43 PCIE30_TX0_P LVDS Output PCIE3 0 data signal output Positive 44 NC Not connected pin 45 GND GND Ground 46 NC Not connected pin 47 PCIE30_RX0N LVDS Input PCIE3 0 data signal input Negative 48 NC N...

Page 15: ...6 NC Not connected pin 7 NC Not connected pin 8 UIM_PWR PWR Input SIM power supply 9 GND GND Ground 10 UIM_DATA IO Input SIM data signal 11 NC Not connected pin 12 UIM_CLK IO Input SIM clock signal 1...

Page 16: ...connected pin 50 GND GND Ground 51 NC Not connected pin 52 3 8V PWR Output 3 8V 3A Max in total 2 19 U 2 Pin Pin Name Pin Type Input Output Signal Description 1 GND GND Ground 2 SATA0_SSRXP LVDS Inpu...

Page 17: ...GND Ground 36 GMAC0_MDC IO Output GMAC management interface clock 37 GMAC0_RXDV_CRS IO Input RGMII signal 38 GND GND Ground 39 NC Not connected pin 40 NC Not connected pin 41 GND GND Ground 42 NC Not...

Page 18: ...al Description 1 ADC_VIN3 ANA Input Measure external voltage 1 8V Max 2 I2C0_SCL IO Output I2C clock signal 3 I2C0_SDA IO I O I2C data signal 4 GND GND Ground 5 GND GND Ground 6 GND GND Ground 7 NC No...

Page 19: ...Copyright 2021 MIXTILE 4 Support 4 1 Technical Support MIXTILE technical support team assists you with the questions you may have Contact us with the following methods below Email support mixtile com...

Page 20: ...ay cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to r...

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