FLY E185
Service Manual
3.2.2.4 Timing Generator
Timing is the most critical issue in GSM/GPRS applications. The TDMA timer provides a simple
interface for the MCU to program all the timing-related events for receive event control, transmit
event control and the timing adjustment. Detailed descriptions are mentioned in below figure:
Figure: The block diagram of TDMA timer
The TDMA timer unit is composed of three major blocks: Quarter bit counter, Signal generator
and Event registers. By default, the quarter-bit counter continuously counts from 0 to the wrap
position. In order to apply to cell synchronization and neighboring cell monitoring, the wrap
position can be changed by the MCU to shorten or lengthen a TDMA frame. The wrap position is
held in the TDMA_WRAP register and the current value of the TDMA quarter-bit counter may be
read by the MCU via the TDMA_TQCNT register.
The signal generator handles the overall comparing and event-generating processes. When a match
has occurred between the quarter bit counter and the event register, a predefined control signal is
generated. These control signals may be used for on-chip and off-chip purposes. Signals that
change state more than once per frame make use of more than one event register.
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