Fluke PM6685, Service Manual

Page: 23 / 94

of transistor Q2. This point is common to the high and low frequency
paths.
A buffer amplifier with high driving capacity is used to get a linear
output in the 100 W load resistor R106 over a swing of 2 V. This am-
plifier consists of a driver stage Q2, an output stage Q13, and a cur-
rent generator Q4.
From the output of this second amplifier stage, the signal is fed back
to the op amp pin 3 via the divider chain R29 to R32. The trimmer po-
tentiometer R31 sets the gain of the low-frequency path equal to the
high-frequency gain of about 0.9. Capacitor C5 is connected to oper-
ational amplifier pins #1 and #8 to achieve stable operation. The
trimmer potentiometer R33 between pins #1 and #5 on the opera-
tional amplifier is used for adjusting the offset voltage of the opera-
tional amplifier.
The channel A filter connected to the output of the second amplifier
stage is a 100 kHz low-pass LC filter. It consists of the coil L1 and the
two capacitors C18 and C19 in parallel. The filter is controlled by the
relay K4. The filter output is connected to the input of the comparator
stage.
n
Comparator Stage
The comparator stage converts the analog signal from the impedance
converter stage to a square wave. This circuit consists mainly of the
high-speed integrated comparators U8A and U8B plus a separate
trigger level circuit connected to the comparators at pins 9 and 13 via
resistors R87 and R88.
The trigger level circuits, which are described later, generate a DC
level in the range of approximately æ1.6 V. This covers a dynamic
range of 6.4 V since the input signal is divided by a factor of 2 before
it reaches the comparator.
The counter is provided with adjustable hysteresis, i.e., it is control-
lable via the front panel or GPIB. The circuitry for setting the hyster-
esis consists of the resistor network R91 to R96, supplied with +5 V
and –5.2 V. It is connected to the latch enable inputs of the compara-
tor, pin 5 and 7 for Comparator I and pin 17 and 15 for Comparator II.
The input signal is fed to both comparators, the outputs of which are
used for setting/resetting the Flip-Flop U9.
n
Buffer Stage
Before the signal is fed further into the ASIC U29, it has to be
level-shifted by a buffer stage. The negative ECL logic levels
(~ –0.9 V to ~ –1.7 V) from U9 pins 17 and 18, are converted to a
single-ended signal with CMOS logic levels ( ~ 5 V to ~ 0 V).
The buffer is a differential amplifier consisting of the two transistors
Q32 and Q33 whose bases are fed differentially from the two com-
parator outputs. Resistor R304 serves as a current generator that is
switched alternately to the two collector resistors R296 and R297.
Trigger Level Circuits
The trigger level circuits generate the trigger voltage levels to the in-
put comparators. The trigger level range is –3.2 V to + 3.2 V with a
maximum resolution of 0.6 mV. The input amplifier attenuation is
Hardware Functional Description 4-7
U8A
U9
U9
U8B
- 5.2
+5
Q32
Q33
R297
R296
T o
C ou nter
cir cu its
Flip -
Flo p
+ 5
- 5.2
R93
R94
Trig ger Level I
Tri gger Level II
Input si gnal
A
B
C
D
E
F
G
A
B
C
D
E
G
F
F
R91
R92
R96
R87
R88
TP27 TP26
+
-
+
-
R304
Fig. 4-8
Comparator flip-flop and buffer stages.