Fisher PH-DTA300M, Service Manual

Page: 11 / 18

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X-Pointer
register
1 2 3 4 5 6 7 13 12 11 10 9 8
17
18
19
20
21
22
23
24
25
26
27
28
29
30
/RESET MiMD AD0 AD1 MiDio /MiCK AD2 LRCKiA BCKiA SDi0
AD4 AD3
SDo
VDD
Lo
VRAL
VDAL
VDAR
VRAR
STANDBY
Ro
CKS
VSSL
Bus
Switch
Microcom. I/F
XRAM YRAM CROM
register
A1
MX MY MZ AX AY
round & limit
MAC ALU
round & limit
X0 X1 X2
Y0 Y1 Y1
40bit
Address Calc.
2sets
X-Bus
Y-Bus
I-Bus
ERAM
2k word
A0 A2
A3
Y-Pointer
register
C-Pointer
register
Audio I/F
Instruction
Decoder
Program
Control
Flag
VSS
VSSR
TESTP
4k word
4kword
*3
4k word
256word
PROM
PRAM
4k*2+2k
=10kword
DAC
14
AD5
15
/CE
16
/oE
31
AD12
32 AD11
48 47 46 45 44 43 42 36 37 38 39 40 41 35 34 33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
io2
io3
io4
VDD
io5
io6
io7
VSSP
PDo
VCoi
VDDP
CKO
VDDX
Xi
Xo
VSSX
VCO
Timing
Generator
General
Input Port
DIT
General
Output Port
SRAM I/F
DAC
Prog.
Start
VDDT
Interrupt
Control
Timer
AD15 AD10
AD9
VDDT
AD8 AD7 AD6 REQ
VSS
AD13 AD14
/WR
AD16
io0 io1
VSS
PIN FUNCTION
PIN
NO.
Sy
mbol I/O
DESCRIPTION OF P IN FUNCT ION Remark
1 /RESET
I
Reset signal i nput terminal(H:Op eration,L:R eset) Reset(MCU)
2 MiMD I
Mode select in put for MC U i nterface (H:I
2
C L:T SB) ì ! î
3 AD0
I
A ddress output-0 for external SRA M A D0(SRA M )
4 AD1
I
A ddress output-1 for external SRA M A D1(SRA M )
5 MiDio I/O Data input and output for MCU i nterface" I
2
C# SDA $ SDA (MCU)
6 /MiCK
I
Clock input for MC U interf ace" I
2
C# SCL $ SCL (MCU)
7 AD2 I
A ddress output-2 for external SRA M A D2(SRA M )
8 VDDT %
Dig ital po wer supply for in terface (3.3V) VDDT (3.3V)
9
S
Do
O
Data output for audio interface SDO
10 AD3 O A ddress output-3 for external SRA M
A D3(SRA M )
11 AD4 O A ddress output-4 for external SRA M
A D4(SRA M )
12 SDi0 I
Data input-0 for audio interf ace SDi(CDP)
13 BCKiA I
Bit clo ck input-A for audio interface BCK(CDP )
14 LRCKiA I
L R clock input-A for audio i nterface L RCK (CDP)
15 AD5 I
A ddress output-5 for external SRA M A D5(SRA M )
16 CE I
Chip enable signal output for external SRA M CE(SRA M)
17 OE I
Enable signal output for external SRA M OE(SRA M)
18 VDD --
Dig ital p ower supply(2.5V ) VDD(2 .5V )
19 STANBY I
Stand-by terminal& (H:ST B, L :Operation) STA BY(MCU)
20 VSS --
Dig ital G ND GND
21 VSSL --
DAC L ch An alog GND GND
22 VRAL --
DAC V ref for L ch V R
23 LO O
DA C L ch analog signal output L O(amp)
24 VDAL --
DA C power supply for L ch(2.5V ) V DA (2.5V )
25 VDAR --
DA C power supply for Rch(2.5V ) V DA (2.5V )
26 RO O DA C Rch analog signal output
RO(amp)
27 VRAR --
DAC V ref for Rch V R
28 VSSR --
DAC Rc h An alog GN D GND
29 TESTP I
Test input (H:T est& L: Normal) ì Lî
30 CKS I
VCO clo ck selection input(! :VC O& L: X I clock) ìH î
31 AD12 O A ddress output-12 for external SRAM
A D12(SRA M )
32 AD11 O A ddress output-11 for external SRAM
A D11(SRA M)
33 AD10 O A ddress output-10 for external SRAM
A D10(SRA M )
34 AD9 O A ddress output-9 for external SRA M
A D9(SRA M )
35 VDDT --
Dig ital po wer supply for in terface(3.3V) VDDT (3.3V)
36 AD8 O A ddress output-8 for external SRA M
A D8(SRA M )
37 AD7 O A ddress output-7 for external SRA M
A D7(SRA M )
38 A D6 O
A ddress output-6 for external SRA M A D6(SRA M )
39 REQ O
Request pi n for in terrupt host REQ(MCU)
40 V SS --
Dig ital G ND GND
41 A D13 O
A ddress output-13 for external SRAM A D13(SRA M )
42 A D14 O
A ddress output-14 for external SRAM A D14(SRA M )
43 WR I
Write signal output for external SRA M W R(SRA M)
44 A D16 O
A ddress output-16 for external SRAM A D16(SRA M )
45 A D15 --
A ddress output-15 for external SRAM A D15(SRA M )
46 io0 I /O
Data I/O- 0 for external SRA M Io0(SRA M )
47 io1 I /O
Data I/O- 1 for external SRA M Io1(SRA M )
48 V SS --
Dig ital G ND GND
49 io2 I /O
Data I/O- 2 for external SRA M Io2(SRA M )
50 io3 I /O
Date I/O- 3 for external SRA M Io3(SRA M )
51 Io4 I /O Data I/O- 4 for external SRA M
Io4(SRA M )
52 VDD --
Dig ital p ower suppl y(2.5V ) VDD(2 .5V )
53 io5 I /O
Data I/O- 5 for external SRA M Io5(SRA M )
54 io6 I /O
Data I/O- 6 for external SRA M Io6(SRA M )
55 io7 I /O
Data I/O- 7 for external SRA M Io7(SRA M )
56 VSSP --
GND f or VCO circ uit GND
57 Pdo O
Phase detector output Pdo
58 V coi I
Controlled voltage input f or VC O circu it V coi
59 VDDP --
Power suppl y for VCO circu i t VDDP (2.5V)
60 Cko O
16.934Mh z clock output pin Cko (CD)
61 VDDX --
Power suppl y for cry stal oscilla tor" 2.5V ) VDDX(2 .5V )
62 X i I
Crystal oscillato r in put X i(1 6.934M Hz)
63 X o O
Crystal oscillato r output Xo
64 VSSX --
GND f or crystal oscillato r GND
IC8001 TC94A02-005 (MP3 DECODER)
IC BLOCK DIAGRAM & DESCRIPTION