Award BIOS Setup
Memory Hole At
When enabled, the memory hole at the
address will be relocated to
the
6MB address range of the ISA cycle when the processor accesses
the
6MB address area.
When disabled, the memory hole at the 15MB address will be treated as a
DRAM cycle when the processor accesses the
address area.
The options are: Enabled, Disabled (Default).
Peer Concurrency
Enable this item to allow the processor to continue its operation while
another
Bus is active.
The options are: Enabled (Default), Disabled.
Delay PCI Transaction
Enable this item to allow the PIIX3 chip to abort the current
master
cycle
and
to accept the new
master request; after it services the new
master request, it reaccepts the orginal
master and returns the
data
phase to the orignal
master. This should enhance the system
performance.
The options are: Enabled, Disabled (Default).
51