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FIBOCOM NL668-LA Series Hardware Guide
Page 36 of 61
Figure 5-12 UART level translate reference 1
The other level
translator
circuit is shown as Figure 5-13, The rest input and output circuit design of
dotted line please refer to solid line part, but pay attention to signal connection direction.
Figure 5-13 UART level translate reference 2
Note:
Level translate circuits is not suitable for applications of baud rates above 460Kbps.
5.6 ADC Interface
NL668-LA series module support two channels ADC interface. Use AT+MMAD command can read the
value of ADC interface. The voltage range of ADC interface is 0.3V to VBAT_BB.
