FastVision FastCamera13, User Manual, Page: 29 / 52

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0xFF FPGA Configuration. Bit 6 is reserved. Other bits are:
7 Read only “Fget8” status. This is high when the sequencer is still running from a prior
operation.
5 FPGA Loaded on write, FPGA Done on read. Writing this bit high indicates that the program
has finished loading the data FPGA and enables the pinsaver muxes. FPGA Done is the
configuration pin function.
4 FPGA M1 on write, FPGA INIT on read. M1 is the configuration mode bit. Other mode bits
are pulled up. Writing 1 sets the Data FPGA into slave serial mode for configuration load by
the Control FPGA. Writing 0 sets the Data FPGA into JTAG mode for configuration by
external Xilinx Parallel Cable. FPGA Init is inverted from the active low configuration /INIT pin.
3 Read only FPGA Data Out. This allows readback functions to be implemented in the future.
2 Write only FPGA Program. This bit is inverted before driving the chip’s active low pin. Setting
this bit to 1 resets the Data FPGA configuration.
1 FPGA Configuration Clock on write, Configuration Timeout on read. Writing this bit directly
affects the FPGA CCLK pin except when the “Fget8” sequencer is running. In that case this bit
enables Flash to FPGA data transfer if it is 1. Running “Fget8” while this bit is 0 will not cause
any changes to the FPGA DIN or CCLK signals. Configuration Timeout goes high if there have
been 16,777,216 CCLK clocks since Program was last asserted. This can be used as a simple
timeout mechanism for a program that only checks the Done and Init status during FPGA
configuration.
0 FPGA Data In on write, Access Test Bit on read. During FPGA configuration this is the serial
data to the Data FPGA. After configuration it could be used as an additional control line to the
Data FPGA. The Access Test Bit toggles on any port read. Thus reading this register twice in
a row will always provide different data. This can be used to test whether the register access
enable signal is active.
Sensor Register Map
All of the following registers can only be accessed when the sensor register write enable signal is set. This
is bit 2 of register 0xfb. Writing these registers will also cause the values to be shadowed in the scratchpad
RAM at whatever page is currently indicated by bits 1 and 0 of register 0xfb. Thus although the registers
themselves are write-only, there is a copy in the scratchpad RAM immediately after writing them. The
scratchpad copy can obviously be overwritten without affecting the sensor registers if the sensor register
write enable bit is off. The layout of these registers intentionally matches the flash state storage.
0x24 Start Pixel, low 8 bits.
0x25 Start Pixel, high 8 bits. This is the leftmost pixel in the ROI. Pixels are numbered from 0 to the
sensor width - 1. This is different from the old ROI settings which worked in pixel clocks. The
sensor control logic handles the conversion from pixels to clocks. If the starting pixel is not a
multiple of the sensor readout width (10 for MV13 or 16 for MV40) there will be some prescan
pixels in the resultant image. In the future we may want to add logic in the data FPGA to mask out
the prescan pixels.
0x26 End Pixel, low 8 bits.
0x27 End Pixel, high 8 bits. This is the rightmost pixel in the ROI. Pixels are numbered from 0 to the
sensor width - 1. This is different from the old ROI settings which worked in pixel clocks. The
sensor control logic handles the conversion from pixels to clocks. If the ending pixel is not one less
than a multiple of the sensor readout width (10 for MV13 or 16 for MV40) there will be some
postscan pixels in the resultant image. In the future we may want to add logic in the data FPGA to
mask out the postscan pixels.
0x28 Start Line, low 8 bits.
0x29 Start Line, high 8 bits. This is the top line in the ROI. Lines are numbered from 0 to the sensor
height - 1. Only lines in the ROI are scanned.
0x2A End Line, low 8 bits.
0x2B End Line, high 8 bits. This is the bottom line in the ROI. Lines are numbered from 0 to the
sensor height - 1. Only lines in the ROI are scanned.