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9VAAV User’s Manual
3-5 CHIPSET FEATURES SETUP
The parameters in this screen are for system designers, service personnel,
and technically competent users only. Do not reset these values unless
you understand the consequences of your changes.
NOTE: This chapter describes all fields offered by Award Software in this
screen. Your system board designer may omit or modify some fields.
Bank 0/1, 2/3, 4/5 DRAM Timing
The DRAM timing of Bank 0/1, 2/3, 4/5, 6/7 in this field is set by the
system board manufacturer, depending on whether the board has fast
paged DRAMs or EDO (extended data output) DRAMs.
The Choice: SDRAM 10ns,SDRAM 8ns,Normal, Medium, Fast, Turbo.
SDRAM Cycle Latency
This field sets the CAS latency timing.
The Choice: 2, 3.
DRAM Clock
This item allows you select DRAM clock.
The choice: Host CLK,HCLK-33M,HCLK+33M.
