Fanstel BlueFan BT680E, Manual, Page: 17 / 30

BlueFan BT680F/E/T BLE5 Module
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Operation mode: I 2 C bus master
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Serial clock frequency: standard mode(100 kHz maximum), fast mode (100 to 400 kHz).
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Output mode: Open drain, CMOS output
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Device address format: 7 bit address, 10 bit address is not supported.
Pulse Width Modulation Interface
Features of PWM interface.
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Utilize VDDIO power supply
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Pulse generation function
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Selectable source clock, 16 MHz or 32.768 kHz
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12 bit clock division setting, divider up to 1/4096: 8Hz to 16.384kHz for 32.768 kHz clock;
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Divider up to 1/16777216, 0.954 Hz to 8MHz for 16 MHz clock.
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It can mask the pulse output with 1 second period, 50 ms unit width (rhythm function).
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The interrupt can be generated in synchronization with the cycle of 1 second rhythm pattern.
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It can switch the pulse output to Low/High active
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Duty of pulse output is adjustable.
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Each PWM output can be synchronized by the pulse output synchronization function.
Analog to Digital Converter
BT680F has 6 channels of 12 bit ADC for battery monitoring and analog inputs from external sensors.
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Utilize VDDIO power supply
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1 internal input channel (ADC 0) for VBAT voltage monitoring.
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5 channels for analog inputs, shared with GPIOs
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Maximum conversion rate is 1 MS/s
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10-bit by default, 12-bit selectable
The ADC has up to 12-bit conversion accuracy and can work for input voltage from 0V to 3.6V (VDD).
ADC channel 0 is connected to the VDDCORE2, whose voltage level is 1.2V, an IC internal voltage.
When a battery is used as power source, the reference voltage can slide over time because the
battery is connected as reference voltage.
AD converted data can be calculated by CPU into voltage values because the channel 0 is supplied
with 1.2V to its input.
Input voltage of ADC 1 to ADC 5 = (conversion result of ADCn/conversion result of ADC0) x1.2V