Fairchild SEMICONDUCTOR AN-7502 Application Note Download Page 3

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Application Note 7502 Rev. A1

State 2: MOS ActIve, JFET ActIve

This state graphically illustrates the dramatic influence that
the JFET has on the power MOSFET drain-voltage wave-
form. Instead of having to discharge C

from V

to ground,

the lateral MOSFET need only swing V

to ground, a much

smaller voltage thanks to the grounded gate JFET. Since the
interaction of R

with the device capacitances has a second-

order effect on the drain voltage, the equivalent circuit of Fig-
ure 7 predicts a drain voltage change of:

/dt = g

/[C

+ C

(1 + g

)]

In all but the smallest power-MOSFET devices, C

is several

thousand picofarads and g

is of the order of 3:1.

Power-MOSFET devices exhibit a high dV

/dt switching rate

because of the cascode-connected JFET, not because
C

RSS

= C

) is a small value, as zero-drain-current

data sheet capacitance values might lead one to believe. If
C

RSS

were, in actuality, small, long drain voltage tails would

not exist. The tail response is a direct result of JFET satura-
tion. In order to delineate the transition from state 2 to state
3, a drain voltage at which the transition occurs must be
defined. V

is the knee voltage at which linear extrapola-

tions of drain-voltage slopes intersect. The time duration of
state 2 is:

) = (V

- V

)[C

+ C

(1 + g

J)]/g

State 3: MOS Active, JFET Saturated

When the JFET saturates, the g

current generator

becomes a short circuit and the equivalent circuit predicts:

/dt = g

/[C

+ C

(1 + g

)]

This is the Miller effect so often referred to in older texts that
describe the behavior of grounded-cathode vacuum-tube
amplifier circuits. Allowing for the fact that 1 + g

approximately equal to g

and C

(1 + g

) is very

much larger than C

, the expression for drain-voltage tail

time is:

) = (V

- V

D(SAT)

State 4: MOS Saturated, JFET Saturated (Turn-Off)

In this state, in addition to g

being shorted, the g

cur-

rent generator is shorted, and I

is occupied with charging C

and C

, in parallel, from the peak value of V

to V

G(SAT)

. The

time required for this is:

= (V

- V

G(SAT)

)(C

+ C

)/I

Since a value for C

may be measured independently of

switching time, the method described is the simplest way of
determining C

On turn-off, the state time equations are equally applicable,
but in reverse order (states 5 and 6); see the idealized wave-
form of Figure 4.

Experimental Verification

The four switching states just analyzed indicate that for a
given device, all four switching state times are inversely pro-
portional to the magnitude of the gate drive current. Figure 8
illustrates the switching performance of a typical power
MOSFET across three decades of gate drive current and
time. In each case the data slope is almost a perfect -1.

A New Device Characterization

Figure 8 could not be a reasonable device data sheet pre-
sentation because it does not give the designer any informa-
tion on a typical value for C

, nor does it convey how V

, g

, and V

(sat) vary with drain current. What would

be of enormous value to the designer is a plot of V

(t), V

(t)

for selected values of V

and I

within device ratings.

A reasonable characterization would be as follows:

1. The x axis would be normalized in terms of gate current drive.

2. The y axis would be normalized in terms of percent maximum rated

DSS

(0 to 100%).

3. R

= BV

DSS

D(max)

would define the drain load resistance.

4. Four plots of V

(t), V

(t) at 100%, 75%, 50%, and 25% BV

DSS(max)

would be shown.

FIGURE 8.

CONSTANT GATE CURRENT SWITCHING TIME

Figure 9 is such a plot for the RFM15N15 power MOSFET.
With such a plot, a designer can estimate device switching
performance under any resistive gate/drain conditions.

0.1

0.01

100

1000

RFM15N15
V

= 75V

= 7.5A
=

∞

Ω

= 10V

) -