© 2012 Fairchild Semiconductor Corporation
8
FEBFL7730_L20H008A • Rev. 0.0.2
5.
Schematic
N1
N3
R
12
510k
C
8
10n
D
4
RS
1M
D
5
ES3D
C
10
35V/
330u
F
1
N2
V
O
CS
GA
T
E
VDD
Di
m
CO
MI
GND
GN
D
VS
7
8
3
6
2
4
5
R
8
150k
R
9
20
k
R
13
10
Ω
R
14
1.2
Ω
D
3
1N4
003
C
5
10p
C
9
4.
7n
F
C
4
1u
L
1
10
m
H
R
15
1.
0
Ω
C
6
2.
2u
R
17
51k
D
2
11
V
R
5
510
k
R
6
200k
R
4
1M
Q1
MB8
S
R
1
1k/
0.
5W
C
1
10
0n
C
2
10
0n
Q
3
F
L
7
730
Q4
F
Q
U2N
60C
R
10
250k
Ω
0.
5W
L
2
4.
7mH
C
7
47
u
F
1
1A/
250
V
R
11
510
k
R
2
300
/0
.5W
D
1
ES1J
R
3
43
k
C
3
1
00n
F
Q2
F
Q
N1
N50C
R
16
0
R
7
0
C
11
35V/
1000
uF
Figure 10.
Schematic of Evaluation Board
