FabiaTech Corporation
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)
MODEM Control Register (MCR)
Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
Line Status Register (LSR)
Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0
MODEM Status Register (MSR)
Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
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Summary of Contents for FX5653
Page 15: ...FabiaTech Corporation g3 FX5622K1 Rack Mount 11 ...
Page 42: ...FabiaTech Corporation Host Bridge Host Bridge Parameters 38 ...
Page 45: ...FabiaTech Corporation South Bridge South Bridge Parameters 41 ...
Page 69: ...FabiaTech Corporation Exit extended function mode Mov dx 2eh Mov al aah Out dx al 65 ...
Page 82: ...FabiaTech Corporation Appendix Dimension a FX5653 250 REF 50 REF 180 REF 78 ...
Page 83: ...FabiaTech Corporation b FX5504K1 61 2 REF 118 REF 75 100 19 REF 7 75 100 75 REF 12 5 8 79 ...
Page 84: ...FabiaTech Corporation c FX5501K1 278 REF 264 REF 58 REF 37 47 140 90 REF 8 10 80 ...
Page 85: ...FabiaTech Corporation 81 d FX5622K1 455 REF 469 REF 480 REF 31 75 44 50 REF ...