Evalue Technology ECM-3610, User Manual

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ECM-3610/3610L
ECM-3610/3610L User’s Manual 59
4.5.4.3 SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset this field from the default value specified by
the system designer.
The Choice: 2, 3.
4.5.4.4 Bank Interleave
Set SDRAM bank interleave.
The Choice: Disabled, 2 Bank, 4 Bank.
4.5.4.5 Memory Hole
In order to improve performance, certain space in memory is reserved for ISA cards. This
memory must be mapped into the memory space below 16MB.
The Choice: 15M-16M, Disabled.
4.5.4.6 P2C/C2P Concurrency
When disabled, CPU bus will be occupied during the entire PCI operation period.
The Choice: Enabled, Disabled.
4.5.4.7 System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting
in better system performance. However, if any program writes to this memory area, a
system error may result.
The choice: Enabled, Disabled.
4.5.4.8 Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance.
However, if any program writes to this memory area, a system error may result.
The Choice: Enabled, Disabled.
4.5.4.9 Frame Buffer Size
Select the size of onboard video controller’s frame buffer. The buffer size are share from
system memory unit.
The Choice: 2M, 4M, 8M, 16M, 32M.