110118-0001A
63
Symbol
Parameter
Min
Typ.
Max
Units
R HP_IN
pull-up to Vcc
100
k
Ω
V HP_IN
threshold voltage
4
V
Notes:
29. The output sample rate is fixed, but the input sample rate can be set to 8, 11.025, 22.05 or
44.1 kHz.
30. Pre-amp anti-aliasing filter rolls off at 3dB/octave (first-order filter)
31. Typical values are guaranteed to National Semiconductor's AOQL (Average Outgoing
Quality Level). Operating above typical values for a sustained period of time may result in
thermal shutdown of the amplifier.
6.3.9
PXA270 Processor
The PXA270 core can change system voltage Vddi (section 6.3.4) dynamically to achieve lower
power consumption at high clock rates. It uses voltage Vddx to power its interface I/Os. The
EIOn digital I/Os include series resistance and ESD protection.
Serial ports configured for 3.3 V logic level operation only run directly to the processor (section
4.5.1). No series resistance or ESD protection is provided. These lines should be treated as digital
I/Os and protected for over-current and over-voltage accordingly. Ferrite beads are included on
Serial 1 and Serial 3 ports with 33
Ω
series resistance added under the 3.3 V logic level production
option.
PXA270 synchronous serial port 3 (SSP3) is available for application use on header J3. Treat the
signals as digital I/Os. The SSP3 signals connect to the CPU through 1k
Ω
series resistors.
Absolute Maximum Ratings
Input voltage, digital I/O pins .....................................3.6 V
Symbol
Parameter
Min
Typ.
Max
Units
Digital Outputs
Vol
0
V
ddx
Voh
1.0
V
ddx
Io
-2
2
mA
Digital Inputs
Vil
0.2
V
ddx
Vih
0.8
V
ddx
EIOn Digital I/Os (J3, 3.3.3 and J10, 3.3.8)
Reio
EIOn series resistance
1
k
Ω
I2C Bus (4.5.4)
bus clock (note 34)
100
400
kHz
buffer size
1
byte
Rbus
pull-up on SDA, SCK
4.7
4.99
k
Ω
Vbus
3.3
V
USB Host Port
R_pwr_sense
USB_PWR_SENSE Pull-up to Vddx
47
k
Ω
Notes:
32. The PXA270 supports "standard" and "fast" I2C speeds of 100 and 400 kHz.
