Schematic Diagrams
ICH7-1 B - 15
B.Schematic Diagrams
ICH7-1
Sheet 14 of 40
ICH7-1
+VCCRTC
+VDD5
+VCCRTC
+VCCRTC
+3VS
+1.05VS
+1.05VS
SATALED#
27
SATATXN0
18
SATATXP0
18
SATARXN0
18
SATARXP0
18
CLK_PCIE_SATA#
2
CLK_PCIE_SATA
2
IDE_PDIOR#
18
IDE_PDIOW#
18
IDE_PDDACK#
18
INT_IRQ14
18
IDE_PIORDY
18
IDE_PDDREQ
18
RSVD9 15
LPC_AD[3:0] 23,26,33
LPC_DRQ#0 23,33
LPC_FRAME# 23,26,33
H_CPUSLP# 3,5
H_A20M# 3
H_DPRSTP# 3,32
H_DPSLP# 3
H_FERR# 3
H_IGNNE# 3
FWH_INIT# 26
H_INIT# 3
H_INTR 3
H_RCIN# 16,23
H_NMI 3
H_SMI# 3
H_STPCLK# 3
PM_THRMTRIP# 3,6,23
IDE_PDA[2:0] 18
IDE_PDD[15:0] 18
IDE_PDCS1# 18
IDE_PDCS3# 18
+1.05VS 2,3,4,5,9,17,32
+VDD5 23,26,27,29,30,32,34
+3VS 2,3,6,9,11,12,13,16,17,18,19,20,21,23,24,25,26,27,28,30,32,33,34
+3V 15,16,17,20,21,23,25,28,29,30,34
+VCCRTC 17
H_A20GATE 23
+3VH8 22,23,25,31,34
+5VS 16,17,18,22,23,24,25,27,29,30,32,33,34
ACZ_BITCLK
34
ACZ_SYNC
34
ACZ_RST#
34
ACZ_SDATAOUT
34
ACZ_SDATAIN0
34
ACZ_SDATAIN1
34
H_PWRGD 3
Z1408
Z1407
Z1402
SM_INTRUDER#
Z1401
Z1404
Z1403
RTC_RST#
SM_INTRUDER#
ICH_INTVRMEN
Z1411
ACZ_SDATAIN1
ACZ_RST#
ACZ_SDATAIN0
ACZ_BITCLK
ACZ_SDATAOUT
ACZ_SYNC
Z1421
Z1422
Z1423
Z1424
Z1425
Z1426
ACZ_SDATAIN2
SATALED#
Z1427
Z1428
Z1430
Z1429
CLK_PCIE_SATA
Z1431
CLK_PCIE_SATA#
Z1409
Z1410
Z1412
Z1413
Z1414
Z1415
Z1416
Z1417
Z1418
Z1419
Z1420
IDE_PIORDY
ICH_INTVRMEN
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#1
Z1432
Z1433
H_FERR#
Z1437
Z1435
Z1436
IDE_PDD0
IDE_PDD1
IDE_PDD3
IDE_PDD2
IDE_PDD5
IDE_PDD4
IDE_PDD7
IDE_PDD6
IDE_PDD9
IDE_PDD8
IDE_PDD11
IDE_PDD10
IDE_PDD13
IDE_PDD12
IDE_PDD15
IDE_PDD14
IDE_PDA1
IDE_PDA0
IDE_PDA2
Z1434
SATALED#
Z1405
Z1406
IDE_PIORDY
ACZ_SDATAOUT
C530
3900P
R513
39
R489
0
R511
39
R514
39
R488
0
R486
24_1%
R487
0
R104
56
C527
3900P
R485
*0
R492
10K
RT
C
LA
N
AC
-9
7/
AZ
AL
IA
SA
TA
IDE
LPC
U36A
ICH7-M
AB1
AB2
AA3
Y5
W4
W1
Y1
Y2
W3
V3
U3
U5
V4
T5
U7
V6
V7
U1
R6
R5
T2
T3
T1
T4
AF18
AF3
AE3
AG2
AH2
AF7
AE7
AG6
AH6
AF1
AE1
AH10
AG10
AF15
AH15
AF16
AH16
AG16
AE15
AA6
AB5
AC4
Y6
AC3
AA5
AB3
AE22
AH28
AG27
AF24
AH25
AG26
AG24
AG22
AG21
AF22
AF25
AG23
AH24
AF23
AH22
AF26
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AH17
AE17
AF17
AE16
AD16
RTCX1
RTCX2
RTCRST#
INTRUDER#
INTVRMEN
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
ACZ_BIT_CLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_SDOUT
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATARBIASP
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#/GPIO23
LFRAME#
A20GATE
A20M#
CPUSLP#
TP1/DPRSTP#
TP2/DPSLP#
FERR#
GPIO49/CPUPWRGD
IGNNE#
INIT3_3V#
INIT#
INTR
RCIN#
NMI
SMI#
STPCLK#
THERMTRIP#
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
DA0
DA1
DA2
DCS1#
DCS3#
D12
RB751V
A
C
R510
39
R132
39
R180
1M
Y4
32.768KHZ
1
3
2
4
C124
1UF
R109
20K
C622
0.1U_04
R184
2K 1%
R185
750 1%
R183
560
C220
*1UF
R495
24.9_1%
R188
1K
R519
39
D10
RB751V
A
C
R611
1K_0402
J4
JOPEN
2
1
R105
56
C542
10PF
C531
10PF
R509
332K_1%
R517
*1K
R504
10M
R136
*1K
R99
4.7K
R508
*0
JBAT1
CON2_BAT
1
2
1
2
Layout note:R6V12
needs to placed within
2" of ich7.RV164 must
be placed within 2" of
R6V12 W/O stub.
Distance between the ICH7 M and
cap on the "P" signal should be
indentical distance between the
ICH7-M and cap on the "N"signal
same pair.
Short pins AH10 and AG10 at the
package.Place R7H1 winthin 500
mils of ICH7 BALL
Enable(default)
Disable
INTVRMEN
1
0
R7V1
R7V2
STUFF
UNSTUFF
UNSTUFF
STUFF
F950103
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