ETAS XETK-S21.0B, User Manual

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XETK-S21.0B - User’s Guide 40
Technical Data ETAS
7.7 Test Characteristics
1)
Delay of ECU reset through the XETK without transferring the FPGA (U
Batt
pres-
ent, VDDP will be switched on)
2)
max. delay of ECU reset through the XETK (U
Batt
and VDDP will be switched on)
7.8 JTAG Timing Characteristics
The following diagrams show the timings the XETK-S21.0 can process.
7.8.1 JTAG Timing Diagram
Parameter Symbol Condition Min Typ Max Unit
Reset delay 1
1)
t
Reset1
U
Batt
= 12 V

VDDP = 0 V

3.3 V/
5.0 V

without transferring
FPGA
29 40 ms
Reset delay 2
2)
t
Reset2
U
Batt
= 0 V

12 V

transfer FPGA
200 340 ms
Note
JTAG timing parameters in this chapter refer to the JTAG interface (CON6) of
the XETK-S21.0. The JTAG wiring to the ECU (ETAI10) must be taken into
account additionally.

All timings are measured at a reference level of 1.5 V. Output signals are mea-
sured with 20 pF to ground and 50

to 1.5 V.