ETK-S21.1 - User’s Guide
15
ETAS GmbH
Introduction
– Data rate160 Mbit/s, 320 Mbit/s
– 3.3 V ECU interface voltage level
– ETK powers Emulation Device RAM
– 50 pin ERNI plus 5 pin JST
• Trigger interface
– Pinless trigger via JTAG or LFAST (32 total measurement rasters)
– 4 triggers generated by internal timers
• Debugger interface (JTAG mode only)
– additional connector for external debug hardware
– ETK hardware is prepared to be used simultaneously with a debugger
• Startup protocol for ETK/ ECU synchronization
– via JTAG pins
– via JTAG Data Communication (JDC) feature
• Supports special coldstart mechanism ("Calibration Wake Up")
– Calibration Wake Up: Wake up mechanism to wake up the power sup-
ply of the ECU via the Calibration Wake up pin
– Pull CalWakeUp until Startup Handshake: duration of the Wake up
mechanism is configurable
• Permanent storage of configuration in EEPROM
• Configuration of ETK via XCT Configuration Tool
• ETK firmware update (update of the ETK hardware definition code [HDC])
supports by service software HSP
• Mounting possibilities inside or on top of ECU
• Temperature range suitable for automotive applications
For more technical data on the ETK-S21.1 consult the chapter "Technical Data"
on page 34.
Note
The max. allowed JTAG clock depends on the core frequency of the micro-
controller. Max. clock speed is 1/4 of the core frequency.