ESMT F25L02PA Series Manual Download Page 6 | Manualshive

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ESMT F25L02PA Series Manual Download Page 6

ESMT

F25L02PA (2F)

Operation Temperature Condition -40

°

C~85

°

C

Elite Semiconductor Memory Technology Inc.

Publication D

ate

:

Jan. 2012

Revision

:

1.0

6/32

Table 3: F25L02PA Block Protection Table

Status Register Bit

Protected Memory Area

Protection Level

TB

BP2

BP1

BP0

Block Range

Address Range

0

X

0

0

0

None

None

Upper 1/4

0

0

0

1

Block 3

030000H – 03FFFFH

Upper 1/2

0

0

1

0

Block 2~3

020000H – 03FFFFH

Upper 3/4

0

1

1

0

Block 1~3

010000H – 03FFFFH

Lower 1/4

1

0

0

1

Block 0

000000H – 00FFFFH

Lower 1/2

1

0

1

0

Block 0~1

000000H – 01FFFFH

Lower 3/4

1

1

1

0

Block 0~2

000000H – 02FFFFH

All Blocks

X

X

1

1

Block 0~3

000000H – 03FFFFH

Block Protection (BP2, BP1, BP0)

The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the

BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to 0.

Block Protection Lock-Down (BPL)

WP pin driven low (V

IL

), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When

the WP pin is driven high (V

IH

), the BPL bit has no effect and its

value is “Don’t Care”. After power-up, the BPL bit is reset to 0.

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Summary of Contents for F25L02PA Series

Page 1: ...0PIG2F 100MHz 8 lead SOIC 150 mil Pb free F25L02PA 50PAIG2F 50MHz F25L02PA 86PAIG2F 86MHz F25L02PA 100PAIG2F 100MHz 8 lead SOIC 200 mil Pb free F25L02PA 50HIG2F 50MHz F25L02PA 86HIG2F 86MHz F25L02PA 100HIG2F 100MHz 8 contact WSON 6x5 mm Pb free GENERAL DESCRIPTION The F25L02PA is a 2Megabit 3V only CMOS Serial Flash memory device The device supports the standard Serial Peripheral Interface SPI and...

Page 2: ...on 40 C 85 C Elite Semiconductor Memory Technology Inc Publication Date Jan 2012 Revision 1 0 2 32 PIN CONFIGURATIONS 8 Lead SOIC SOIC 8L 150mil Body 1 27mm Pin Pitch SOIC 8L 208mil Body 1 27mm Pin Pitch 1 8 2 7 3 6 4 5 VDD HOLD SCK SI CE SO WP VSS ...

Page 3: ...er commands addresses or data serially into the device Data is latched on the rising edge of SCK SO Serial Data Output To transfer data serially out of the device Data is shifted out on the falling edge of SCK CE Chip Enable To activate the device when CE is low WP Write Protect The Write Protect WP pin is used to enable disable BPL bit in the status register HOLD Hold To temporality stop serial c...

Page 4: ...Decoder I O Butters and Data Latches Serial Interface Control Logic CE SCK SI WP SO HOLD SECTOR STRUCTURE Table 1 F25L02PA Sector Address Table Block Address Block Sector Sector Size Kbytes Address range A17 A16 63 4KB 03F000H 03FFFFH 3 48 4KB 030000H 030FFFH 1 1 47 4KB 02F000H 02FFFFH 2 32 4KB 020000H 020FFFH 1 0 31 4KB 01F000H 01FFFFH 1 16 4KB 010000H 010FFFH 0 1 15 4KB 00F000H 00FFFFH 0 0 4KB 0...

Page 5: ...d only bits 0 BP2 BP1 BP0 and TB are read writable 0 R W Note 1 Only BP0 BP1 BP2 TB and BPL are writable 2 BP0 BP1 BP2 TB and BPL are non volatile 3 All area are unprotected at power on BP2 BP1 BP0 0 WRITE ENABLE LATCH WEL The Write Enable Latch bit indicates the status of the internal memory Write Enable Latch If this bit is set to 1 it indicates the device is Write enabled If the bit is set to 0...

Page 6: ...000000H 03FFFFH Block Protection BP2 BP1 BP0 The Block Protection BP2 BP1 BP0 bits define the size of the memory area as defined in Table 3 to be software protected against any memory Write Program or Erase operations The Write Status Register WRSR instruction is used to program the BP2 BP1 BP0 bits as long as WP is high or the Block Protection Look BPL bit is 0 Chip Erase can only be executed if ...

Page 7: ...an be VIL or VIH If CE is driven active high during a Hold condition it resets the internal logic of the device As long as HOLD signal is low the memory remains in the Hold condition To resume communication with the device HOLD must be driven active high and CE must be driven active low See Figure 22 for Hold timing A ctive H o ld A cti ve H old A ctive H O L D S C K Figure 1 HOLD Condition Wavefo...

Page 8: ... SIN SOUT Read 33 MHz 03H Hi Z A23 A16 Hi Z A15 A8 Hi Z A7 A0 Hi Z X DOUT0 X DOUT1 X cont Fast Read 13 50 MHz 100 MHz 0BH Hi Z A23 A16 Hi Z A15 A8 Hi Z A7 A0 Hi Z X X X DOUT0 X cont Fast Read Dual Output 11 12 50MHz 86 MHz 3BH A23 A16 A15 A8 A7 A0 X DOUT0 1 cont Sector Erase 4 4K Byte 20H Hi Z A23 A16 Hi Z A15 A8 Hi Z A7 A0 Hi Z Block Erase 4 64K Byte D8H Hi Z A23 A16 Hi Z A15 A8 Hi Z A7 A0 Hi Z C...

Page 9: ...on and the Write Status Register WRSR instruction must work in conjunction of each other The WRSR instruction must be executed immediately very next bus cycle after the WREN instruction to make both instructions effective WREN can enable WRSR user just need to execute it A successful WRSR can reset WREN 10 The Manufacture ID and Device ID output will repeat continuously until CE terminates the ins...

Page 10: ... location 000000H The Read instruction is initiated by executing an 8 bit command 03H followed by address bits A23 A0 CE must remain active low for the duration of the Read cycle See Figure 2 for the Read sequence Figure 2 Read Sequence Fast Read 50 MHz 100 MHz The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8 bit command 0BH followed by address bits A23 A0 and a du...

Page 11: ...s data to be transferred from the device at twice the rate of standard SPI devices This instruction is for quickly downloading code from Flash to RAM upon power up or for applications that cache code segments to RAM for execution The Fast Read Dual Output instruction is initiated by executing an 8 bit command 3BH followed by address bits A23 A0 and a dummy byte CE must remain active low for the du...

Page 12: ...ast significant bits A7 A0 are all zero If more than 256 bytes Data are sent to the device previously latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page If less than 256 bytes Data are sent to device they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page CE must be dr...

Page 13: ... of the internal self timed Block Erase cycle See Figure 8 for the Block Erase sequence Figure 8 64K byte Block Erase Sequence 4K Byte Sector Erase The Sector Erase instruction clears all bits in the selected sector to FFH A Sector Erase instruction applied to a protected memory area will be ignored Prior to any Write operation the Write Enable WREN instruction must be executed CE must remain acti...

Page 14: ... the completion of the internal self timed Chip Erase cycle See Figure 10 for the Chip Erase sequence Figure 10 Chip Erase Sequence Read Status Register RDSR The Read Status Register RDSR instruction allows reading of the status register The status register may be read at any time even during a Write Program Erase operation When a Write operation is in progress the Busy bit may be checked before s...

Page 15: ...st be executed prior to any Write Program Erase operation CE must be driven high before the WREN instruction is executed Figure 12 Write Enable WREN Sequence Write Disable WRDI The Write Disable WRDI instruction resets the Write Enable Latch bit to 0 disabling any new Write operations from occurring CE must be driven high before the WRDI instruction is executed Figure 13 Write Disable WRDI Sequenc...

Page 16: ... down the status register but cannot be reset from 1 to 0 When WP is high the lock down function of the BPL bit is disabled and the BPL TB BP0 BP1 and BP2 bits in the status register can all be changed As long as BPL bit is set to 0 or WP pin is driven high VIH prior to the low to high transition of the CE pin at the end of the WRSR instruction the bits in the status register can all be altered by...

Page 17: ...lti purpose instruction The instruction can be used to release the device from the deep power down status This instruction is initiated by driving CE low and executing an 8 bit command ABH and then drive CE high See Figure 16 for RDP instruction Release from the deep power down will take the duration of TRES1 before the device will resume normal operation and other instructions are accepted CE mus...

Page 18: ...tronic Signature RES Sequence Table 6 Electronic Signature Data Command Electronic Signature Data RES 11H SCK 0 1 2 3 4 5 6 7 MODE3 MODE0 SI CE Standby Current TRES1 MSB AB Deep Power Down Current ISB2 SO HIGH IMPEDANCE SCK 0 1 2 3 4 5 6 7 8 9 MODE3 MODE0 SI CE Standby Current TRES2 MSB AB Deep Power Down Current ISB2 SO HIGH IMPEDANCE SS 30 31 32 33 34 35 36 37 38 SS Electronic Signature Data Out...

Page 19: ...e manufacturer as ESMT Byte2 30H identifies the memory type as SPI Flash Byte3 12H identifies the device as F25L02PA The instruction sequence is shown in Figure 18 The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output If no other command is issued after executing the JEDEC Read ID instruction issue a 00H NOP command before going into Standby M...

Page 20: ...dress 000000H and the device ID is located in address 000001H Once the device is in Read ID mode the manufacturer s and device ID output data toggles between address 000000H and 000001H until terminated by a low to high transition on CE Figure 19 Read ID Sequence Table 8 Product ID Data Address Byte1 Byte2 8CH 11H 000000H Manufacturer s ID Device ID ESMT F25L02PA 11H 8CH 000001H Device ID ESMT F25...

Page 21: ...n one second No more than one output shorted at a time AC CONDITIONS OF TEST OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 2 3 3 6 V Ambient Operating Temperature TA 40 85 Table 9 DC OPERATING CHARACTERISTICS Limits Symbol Parameter Min Max Unit Test Condition Standard 8 IDDR1 Read Current 33 MHz Dual 10 mA CE 0 1 VDD 0 9 VDD SO open Standard 12 IDDR2 Read Current 50MHz ...

Page 22: ...6 MHz Fast 100 MHz Symbol Parameter Min Max Min Max Min Max Min Max Unit FCLK Serial Clock Frequency 33 50 86 100 MHz TSCKH 2 Serial Clock High Time 13 9 5 4 ns TSCKL 2 Serial Clock Low Time 13 9 5 4 ns TCLCH Clock Rise Time Slew Rate 0 1 0 1 0 1 0 1 V ns TCHCL Clock Fall Time Slew Rate 0 1 0 1 0 1 0 1 V ns TCES 1 CE Active Setup Time 5 5 5 5 ns TCEH 1 CE Active Hold Time 5 5 5 5 ns TCHS 1 CE Not ...

Page 23: ...h to Deep Power Down Mode 3 3 3 3 us TRES1 3 CE High to Standby Mode for DP 3 3 3 3 us TRES2 3 CE High to Standby Mode for RES 1 8 1 8 1 8 1 8 us Note 1 Relative to SCK 2 TSCKH TSCKL must be less than or equal to 1 FCLK 3 Value guaranteed by characterization not 100 tested in production 4 Only applicable as a constraint for a Write status Register instruction when Block Protection Look BPL bit is ...

Page 24: ...2PA 2F Operation Temperature Condition 40 C 85 C Elite Semiconductor Memory Technology Inc Publication Date Jan 2012 Revision 1 0 24 32 Figure 20 Serial Input Timing Diagram Figure 21 Serial Output Timing Diagram ...

Page 25: ...ition 40 C 85 C Elite Semiconductor Memory Technology Inc Publication Date Jan 2012 Revision 1 0 25 32 Figure 22 HOLD Timing Diagram Figure 23 Write Protect setup and hold timing during WRSR when BPL 1 CE SCK SI HIGH IMPENANCE SO TWHSL TSHWL WP ...

Page 26: ...t State Read command is allowed Device is fully accessible Program Erase and Write command is ignored CE must track VCC Figure 24 Power Up Timing Diagram Table 12 Power Up Timing and VWI Threshold Parameter Symbol Min Max Unit VCC min to CE low TVSL 10 us Time Delay before Write instruction TPUW 1 10 ms Write Inhibit Threshold Voltage VWI 1 2 V Note These parameters are characterized only ...

Page 27: ...hnology Inc Publication Date Jan 2012 Revision 1 0 27 32 Figure 25 AC Input Output Reference Waveforms Figure 26 A Teat Load Example Input timing reference level Output timing reference level 0 8VCC 0 2VCC 0 7VCC 0 3VCC 0 5VCC AC Measurement Level Note Input pulse rise and fall time are 5ns ...

Page 28: ...m Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max A 1 35 1 60 1 75 0 053 0 063 0 069 D 4 80 4 90 5 00 0 189 0 193 0 197 A1 0 10 0 15 0 25 0 004 0 006 0 010 E 3 80 3 90 4 00 0 150 0 154 0 157 A2 1 25 1 45 1 55 0 049 0 057 0 061 L 0 40 0 66 0 86 0 016 0 026 0 034 b 0 33 0 406 0 51 0 013 0 016 0 020 e 1 27 BSC 0 050 BSC c 0 19 0 203 0 25 0 0075 0 008 0 010 L1 1 00 ...

Page 29: ...imension in mm Dimension in inch Symbol Min Norm Max Min Norm Max Symbol Min Norm Max Min Norm Max A 2 16 0 085 E 7 70 7 90 8 10 0 303 0 311 0 319 A1 0 05 0 15 0 25 0 002 0 006 0 010 E1 5 18 5 28 5 38 0 204 0 208 0 212 A2 1 70 1 80 1 91 0 067 0 071 0 075 L 0 50 0 65 0 80 0 020 0 026 0 032 b 0 36 0 41 0 51 0 014 0 016 0 020 e 1 27 BSC 0 050 BSC c 0 19 0 20 0 25 0 007 0 008 0 010 L1 1 27 1 37 1 47 0...

Page 30: ...ETAIL B DETAIL A D2 Symbol Dimension in mm Dimension in inch Min Norm Max Min Norm Max A 0 70 0 75 0 80 0 028 0 030 0 031 A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 35 0 40 0 45 0 014 0 016 0 018 D 5 90 6 00 6 10 0 232 0 236 0 240 D2 2 50 2 60 2 70 0 098 0 102 0 106 E 4 90 5 00 5 10 0 193 0 197 0 201 E2 2 10 2 20 2 30 0 083 0 087 0 091 e 1 27 BSC 0 050 BSC L 0 55 0 60 0 65 0 022 0 024 0 026 Controlli...

Page 31: ...F25L02PA 2F Operation Temperature Condition 40 C 85 C Elite Semiconductor Memory Technology Inc Publication Date Jan 2012 Revision 1 0 31 32 Revision History Revision Date Description 1 0 2012 01 18 Original ...

Page 32: ...f patents copyrights or other intellectual property rights of third parties which may result from its use No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of ESMT or others Any semiconductor devices may have inherently a certain rate of failure To minimize risks associated with customer s application adequate design and op...

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