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ESD V.2031.01 Hardware Manual Download Page 9

Overview

 

 

XMC-CPU/Zulu

  

 Hardware Manual Doc.-Nr.: V.2031.21/ 1.0 

Page 9 of 45 

 

 

1  Overview 

 

 

Figure 1: 

Block circuit diagram 

64-Bit XMC ARM

®

 Host CPU 

The  XMC-CPU/Zulu  in  XMC  form  factor  comes  with  a  XILINX

®

  Zynq

®

  Ult

TM

  CG 

multiprocessor system-on-chip with 1.3 GHz core frequency.  
The local memory bus has a bus width of 32 bits and an overall capacity of 1 Gbyte.  
64 Mbyte SPI Flash for boot loader and 32 Kbit I²C EEPROM for U

‑

Boot environment. 

XMC-CPU/Zulu  features  a  16-Gbyte  eMMC

TM

  memory  which  is  used  for  operating  system,  file 

system and application software. 
 
The XMC interface comes with quad-lane PCIe

®

 bus and is designed according to VITA

TM

 42.3.  

 
Two Gigabit Ethernet interfaces are accessible via the front panel of the XMC-CPU/Zulu. This gives 
an excellent base for EtherCAT

®

 applications.  

Two additional rear IO Ethernet interfaces are accessible via the XMC connector P6. The rear IO 
Ethernet interfaces come without electrical isolation. 
Two of the GB Ethernet interfaces (one front, one rear) are rooted through the FPGA. Therefore, 
special Ethernet IP-cores can be implemented.  
 
A serial interface, designed as terminal interface, is accessible via an USB Mini type-B connector on 
the front.  
 
The Fla

sh memory carries the standard boot program “Das U-Boot” and enables the XMC-CPU/Zulu 

to boot various operating systems from on-board Flash, network or eMMC. 
Board  support  packages  are  available  for  Linux

®

  and  VxWorks

®

.  The  BSPs  include  an  example 

source code for the FPGA. Programming of the FPGA is done via XILINX Toolchain. 
 
The esd EtherCAT Master Stack is available for various operating systems. 
 

 

CPU

Xilinx Zynq Ult

XCZU2CG 

Environment

EEPROM

SPI0

SPI1

8

Dual Quad SPI

1 - 4 GByte Embedded 

System Memory

x32

HP-IO

Bank

64 + 65

1/2 HP-IO

Bank

66

VREF

24x LVDS_18

or 48x LVCMOS18

7x LVDS_18

or 14x LVCMOS18

24x LVCMOS18

or 24x LVCMOS33

Bank 504

P4

P6

P5

Bank

505

10/100/1000

Ethernet

Phy

RGMII-PL

PCIe x4

RGMII-PS

CLK

Bank

502

RGMII-PS

Pinnout
according
to VITA 42.0
Table 5-4
(incl. GND
Connections)

4x2

4x2

24x1

19x2

24x2

7x2

I2C0

3 x Temp.

Sensor, one
with ALERT

4x2

EMMC

Bank 500

Bank

503

MODE
Status
Reset
CLK

Bank

0

Sysmon

RS232

to

USB

SER (RX, TX)

Electrical

isolation

uSD

Bank

501

to P4

I2C1

to

CPU

RGMII-PL

4x2

1/2 Bank

66

19x LVDS_18

or 38x LVCMOS18

RGMII-PL

RGMII-PS

I/O

Expander

I2C

Mux

0R

PMIC

I2C1

MAC ID

EEPROM

(1.8V)

(1.8V)

(1.8V)

(1.2V)

(1.8V)

(1.8V)

(1.8V)

(3.3V)

(1.8V)

(1.8V)

(0,85V + 1.8V)

Physical

Interface

5x Tricolor

LED

LED

Driver

Bank

26

(1.8/3.3V)

VCC

Switch

Physical

Interface

I2C3

I2C1

1,8V

3,3V

0R

FET

Bus

Switch

0R

Fallback

Enable TTL

Physikal Interface to P4

8x

8x

Enable LVDS

74CB3Q3345 o.ä.

TXS0108E o.ä.

10/100/1000

Ethernet

Phy

10/100/1000

Ethernet

Phy

10/100/1000

Ethernet

Phy

VREF

VREF

1x per 
8 channels

1x per 
8 channels

JTAG

1.1 Description of XMC-CPU/Zulu 

Summary of Contents for V.2031.01

Page 1: ...XMC CPU Zulu Hardware Manual Doc Nr V 2031 21 Rev 1 0 Page 1 of 45 XMC CPU Zulu XMC UltraScale TM Zynq MPSoC Board with integrated FPGA Hardware Manual to Product V 2031 01 ...

Page 2: ...ademarks product names company names or company logos used in this manual are reserved by their respective owners Notes The information in this document has been carefully checked and is believed to be entirely reliable esd electronics makes no warranty of any kind with regard to the material in this document and assumes no responsibility for any errors that may appear in this document In particul...

Page 3: ...e of print 2021 03 09 Document type number DOC0800 Hardware version 1 0 Software version 1 0 Document History The changes in the document listed below affect changes in the hardware as well as changes in the description of the facts only Rev Chapter Changes versus previous version Date 1 0 First English manual 2021 03 09 Technical details are subject to change without further notice ...

Page 4: ...so include a warning relating to property damage DANGER Danger statements indicate a hazardous situation which if not avoided will result in death or serious injury WARNING Warning statements indicate a hazardous situation that if not avoided could result in death or serious injury CAUTION Caution statements indicate a hazardous situation that if not avoided could result in minor or moderate injur...

Page 5: ...dling Do not operate the XMC CPU Zulu adjacent to heat sources and do not expose it to unnecessary thermal radiation Ensure an ambient temperature as specified in the technical data DANGER Hazardous Voltage Risk of electric shock due to unintentional contact with uninsulated live parts with high voltages inside of the system into which the XMC CPU Zulu is to be integrated All current circuits whic...

Page 6: ...in accordance with regulations or disregard of safety instructions and warnings The XMC CPU Zulu is intended for installation on a base board according to Vita 42 3 standard The operation of the XMC CPU Zulu in hazardous areas or areas exposed to potentially explosive materials is not permitted The operation of the XMC CPU Zulu for medical purposes is prohibited Service Note The XMC CPU Zulu does ...

Page 7: ...S 23 6 4 Ethernet Interface PL 23 6 5 USB Console Port CON 24 6 6 PCIe Interfaces 24 6 7 Digital Inputs Outputs P4 25 6 8 Digital Inputs Outputs P6 25 6 9 Control Elements and Display Elements 26 6 10 Health 26 6 11 Mass Storage 26 6 12 MicroSD Card Slot 27 6 13 Optional Interfaces 27 6 13 1CAN Interfaces 27 6 13 2PMC Interface 27 7 Connector Assignments 28 7 1 PMC XMC Connectors 28 7 1 1 PMC P1 C...

Page 8: ... of the USB console port 24 Table 13 Data of the PCIe interface 24 Table 14 Data of the Digital I Os on P4 25 Table 15 Data of the Digital I Os on P6 25 Table 16 Data of the control elements and display elements 26 Table 17 Health unit 26 Table 18 Data of the mass storage unit 26 Table 19 Data of the MicroSD card slot 27 Table 20 Data of the optional CAN interfaces 27 Table 21 Data of the optional...

Page 9: ... to boot various operating systems from on board Flash network or eMMC Board support packages are available for Linux and VxWorks The BSPs include an example source code for the FPGA Programming of the FPGA is done via XILINX Toolchain The esd EtherCAT Master Stack is available for various operating systems CPU Xilinx Zynq Ultrascale XCZU2CG Environment EEPROM SPI0 SPI1 8 Dual Quad SPI 1 4 GByte E...

Page 10: ...ther CPU types ZU2EG ZU3CG and ZU3EG are applicable Extended Temperature Range The temperature range can be extended to 40 C up to 75 C PMC PMC according to IEEE Std 1386 2001 instead of XMC interface via connectors P1 and P2 The PCI bus conforms to PCI Local Bus Specification 3 0 32 bit 33 66 MHz 3 3 V 5 V tolerant PCI bus master capability The PMC interface supports 32 bit 66 MHz PCI bus accordi...

Page 11: ... CiA CAN in Automation FPGA Field Programmable Gate Array FSBL First Stage Bootloader HW Hardware I O Input Output LSB Least Significant Bit MSB Most Significant Bit n a not applicable OS Operating System PS Processing System APUs Memory Ethernet etc PL Programmable Logic FPGA RTC Real Time Clock SDK Software Development Kit VIVADO Xilinx development tool for the programming of FPGAs 1 2 Glossary ...

Page 12: ...2 PCB View with Connectors Figure 2 PCB top view The Debug interface X800 must be connected from the bottom side of the XMC CPU Zulu see Figure 3 PCB Bottom Layer Figure 3 PCB bottom view NOTICE Read chapter Hardware Installation on page 19 before you start with the installation of the hardware ...

Page 13: ...Hardware Manual Doc Nr V 2031 21 1 0 Page 13 of 45 See also from page 28 for signal assignment of the CAN connectors For a description of the DIP switch and the SMD tactile switches see page 17 The LEDs are described in chapter LEDs page 14 ...

Page 14: ...the corresponding ETH channel LED Colour Function Indicator State Description SPD yellow Speed ON Ethernet bit rate 1000 Mbit s ACT green Activity flashing Ethernet activity reception and transmission of Ethernet data Table 1 Description of LEDs 3 1 3 Indication of the Tricolor LEDs 0 4 Five Tricolour LEDs are equipped in the front panel LED Colour Description LEDX green User defined via I C bus a...

Page 15: ... link established LED1622 PL GEM U600L routed to PS GEM1 SPD 2 Speed on Ethernet bit rate 1000 Mbit s LED1521 ACT 2 Activity flashing Ethernet activity reception and transmission of Ethernet data LED1520 LNK 2 Link on Ethernet link established LED1522 PS GEM2 U600H SPD 0 Speed on Ethernet bit rate 1000 Mbit s LED1321 ACT 0 Activity flashing Ethernet activity reception and transmission of Ethernet ...

Page 16: ...interface via USB port CON LED410 RX green SER0_RX flashing Receiving data of serial interface via USB port CON LED411 TERM green Terminal flashing Traffic on serial interface via USB port CON TERM LED1222 FPGA LEDs DONE green Done on PL configuration done LED820 ERR red Err Out on Accidental power loss hardware error or PMU failure LED821 STAT green ERR_Stat on Platform Management Unit PMU depend...

Page 17: ... SW800 0 PS_MODE0 The boot mode can be selected according to table 11 1 of the Technical Reference Manual of the Zynq UltraScale Device 1 0 1 PS_MODE1 1 2 PS_MODE2 0 3 PS_MODE3 0 Table 5 MODE switch The PS_MODE switches 0 3 can be set to ON logical value 0 or OFF logical value 1 The values of all switches in the package are interpreted as one number as read from switch 3 to 0 The following table s...

Page 18: ... PROG SRST and POR see Figure 6 page 17 For further information about the reset signals see Technical Reference Manual of the Zynq UltraScale Device 1 Reset Button Pin Direction Description PROG SW820 PS_PROG_B I O PL configuration reset signal SRST SW812 PS_SRST_B Input System reset commonly used during debug POR SW813 PS_POR_B Input Power on reset signal Table 7 Reset signals ...

Page 19: ...s described above 3 Disconnect the system from the mains Make sure that no risk arises from the system into which the XMC CPU Zulu shall be inserted WARNING Hazardous Voltage Risk of electric shock due to unintentional contact with uninsulated live parts with high voltages Disconnect all hazardous voltages mains voltage before opening the system If the system does not have a flexible mains cable b...

Page 20: ... it is not absolutely necessary Fix the XMC CPU Zulu with the screws on the carrier board Use the four M 2 5 x 5 mm screws which are contained in the product package of the module 8 Install the carrier board in your system 9 Connect the Ethernet and the CON interface via the connectors in the front panel of the XMC CPU Zulu 10 Close the system s case again if applicable 11 Connect the system to ma...

Page 21: ... Port 1 CON Mini USB socket type B X1220 MUSB 05 S B SM A mating cycles 1500 Console USB Device PMC P4 XMC P5 XMC P6 64 pin PMC connector P4 mating cycles 100 PMC IO XMC connector Samtec ASP 103614 04 mating cycles 10 PCI Express interface XMC connector Samtec ASP 103614 04 mating cycles 10 e g 73 LVTTL or 34 LVDS I Os Only for test and programming purposes CPU Debug Samtec CLM107 02 F D BE pass t...

Page 22: ...c Cells 94K CLB Flip Flops 47K CLB LUTs RAM Organisation 2 devices each 16 bit no ECC Series 2Gbyte 2x MT40A512M16 Flash memory NOR Organisation 2 devices with Quad SPI Interface Dual Quad SPI 64Mbyte 2x MT25QU256ABA1EW7 0SIT 100 000 read write cycles 20 years data retention Flash memory NAND 16 Gbyte eMMC memory e g Swissbit SFEM4096B1EA1TO I GE 111 E02 EEPROM 1 x 32 Kbit for U Boot Environment 1...

Page 23: ...rface Table 10 Data of the Ethernet interface PS Number of Ethernet interfaces 2 Standard IEEE 802 3 10BASE T 100BASE TX 1000BASE T Bit rate 10 100 1000 Mbit s Controller Integrated in the PS section and routed via the PL Programmable Logic section of the CPU or embedded as IP core in the PL section of the CPU Connection Twisted Pair compatible with IEEE 802 3 1000BASE T Electrical isolation 1x vi...

Page 24: ...ating system driver Connector MiniUSB Type B Table 12 Data of the USB console port Number 1 Controller Integrated in the PS section of the CPU Standard VITA 42 0 Notice The CPU can support PCIe 2 0 If the usage of PCIe 2 0 via the VITA 42 connectors should cause problems it is possible to limit the usage to PCIe 1 1 via software Lanes 4 Mode Device or Root defined by the base board via pin Softwar...

Page 25: ... sheet Bandwidth 3 3V LVTTL max 60 Mbps 1 8 LVDS max 500MHz bandwidth Electrical isolation none Protective circuit none Connector P4 Table 14 Data of the Digital I Os on P4 Number Maximum 62 see chapter XMC P6 I O Connector page 33 for assignment IO Configuration Single ended or differential inputs or outputs depending on FPGA pin configuration Routed as differential pair in the layout Physical in...

Page 26: ...ee XILINX data sheet Temperature 3 CPU internal sensors of the SYSMON unit see XILINX data sheet 3 external I C temperature sensors one with alert output ports XMC IPMI support Not supported Digital IO extension For sideband signals of the PMC XMC bus as e g Root Monarch Wake Reset Connected via an I C IO expander respectively direct to the FPGA Pins Power Management Voltage regulator and clock di...

Page 27: ...and to the PL pins CAN controller acc to ISO 11898 1 Configurable per software from PS or as esdACC IP core integrated in the FPGA section CAN protocol according to ISO 11898 1 Physical Layer external Electrical isolation none if required the CAN interfaces have to be electrically isolated externally Bus termination A terminating resistor has to be set externally if required Connector via P4 Table...

Page 28: ...d 12 13 PCI CLK GND 14 15 GND GNT 16 17 REQ 5V 18 19 VIO AD 31 20 21 AD 28 AD 27 22 23 AD 25 GND 24 25 GND C BE3 26 27 AD 22 AD 21 28 29 AD 19 5V 30 31 VIO AD 17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND n c LOCK 40 41 n c SDONE n c SBO 42 43 PAR GND 44 45 VIO AD 15 46 47 AD 12 AD 11 48 49 AD 09 5V 50 51 GND C BE0 52 53 AD 06 AD 05 54 55 AD 04 GND 56 57 VIO AD 03 58 59 AD 02 AD 01 6...

Page 29: ...E3 14 15 3 3V MODE4 16 17 n c PME GND 18 19 AD 30 AD 29 20 21 GND AD 26 22 23 AD 24 3 3V 24 25 IDSEL AD 23 26 27 3 3V AD 20 28 29 AD 18 GND 30 31 AD 16 C BE2 32 33 GND IDSELB 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD 14 AD 13 46 47 M66EN AD 10 48 49 AD 08 3 3V 50 51 AD 07 n c REQB 52 53 3 3V GNTB 54 55 n c reserved GND 56 57 n c reserved EREADY 58 59 GN...

Page 30: ...N11_GC_65 CLK Input 14 FPGA IO 13 3 3V IO IO_L22N_T3U_N7_DBC_AD0N_65 15 FPGA IO 14 3 3V IO IO_L12P_T1U_N10_GC_65 CLK Input 16 FPGA IO 15 3 3V IO IO_L22P_T3U_N6_DBC_AD0P_65 17 FPGA IO 16 3 3V IO IO_L22N_T3U_N7_DBC_AD0N_66 18 FPGA IO 17 3 3V IO IO_L15N_T2L_N5_AD11N_66 19 FPGA IO 18 3 3V IO IO_L22P_T3U_N6_DBC_AD0P_66 20 FPGA IO 19 3 3V IO IO_L15P_T2L_N4_AD11P_66 21 FPGA IO 20 3 3V IO IO_L24N_T3U_N11_...

Page 31: ..._QBC_AD13P_65 48 FPGA IO 47 3 3V IO TxS 1 RS232 O IO_L22P_T3U_N6_DBC_AD0P_64 49 FPGA IO 48 3 3V IO IO_L16N_T2U_N7_QBC_AD3N_64 50 FPGA IO 49 3 3V IO RxS 0 RS232 I IO_L13N_T2L_N1_GC_QBC_64 CLK Input 51 FPGA IO 50 3 3V IO IO_L16P_T2U_N6_QBC_AD3P_64 52 FPGA IO 51 3 3V IO GND when using SER 1 GND IO_L13P_T2L_N0_GC_QBC_64 CLK Input 53 FPGA IO 52 3 3V IO CLOCK_IN 5V I IO_L14N_T2L_N3_GC_64 CLK Input 54 FP...

Page 32: ...ed 7 unused 7 unused 7 GND 8 GND 8 unused JTAG_TDI 8 GND 8 GND 8 unused 8 unused 9 unused 9 unused 9 unused 9 unused 9 unused 9 GND 10 GND 10 unused JTAG_TDO 10 GND 10 GND 10 unused EEPROM_GA0 10 PCIe_Rx_L0p 11 PCIe_Rx_L0n 11 Unused FPGA BIST 11 PCIe_Rx_L1p 11 PCIe_Rx_L1n 11 unused 11 GND 12 GND 12 unused EEPROM_GA1 12 GND 12 GND 12 GND 12 PCIe_Rx_L2p 13 PCIe_Rx_L2n 13 unused 13 PCIe_Rx_L3p 13 PCI...

Page 33: ..._65 11 FPGA IO 113 IO_L23N_T3U_N9_6 5 11 FPGA IO 145 IO_L8N_T1L_N3_AD 5N_65 11 GND 12 GND 12 FPGA IO 146 IO_L9P_T1L_N4_AD 12P_65 12 GND 12 GND 12 FPGA IO 147 IO_L8P_T1L_N2_AD 5P_65 12 FPGA IO 118 IO_L16P_T2U_N6_Q BC_AD3P_65 13 FPGA IO 116 IO_L16N_T2U_N7_Q BC_AD3N_65 13 FPGA IO 148 IO_L5N_T0U_N9_AD 14N_65 13 FPGA IO 119 IO_L18P_T2U_N10_ AD2P_65 13 FPGA IO 117 IO_L18N_T2U_N11_ AD2N_65 13 FPGA IO 149...

Page 34: ...1 TP1 7 MDI3 TP3 8 MDI3 TP3 S Shield Signal Description MDIx Ethernet data lines x 0 1 Shield case shield connected with the front panel of the XMC CPU Zulu NOTICE Cables of category CAT 5e or higher must be used to grant the function in networks with up to 1000 Mbits s esd grants the EC conformity of the product if the wiring is carried out with shielded twisted pair cables of class SF UTP or hig...

Page 35: ...5 Device connector 5 pin mini USB socket standard type B Pin Position Pin Assignment Pin CON X1220 1 VBUS Input 2 D 3 D 4 5 GND Signal Description VBUS 5 V power supply voltage D D USB signal lines Data Data not connected GND Reference potential 2 1 5 3 4 7 3 USB Console Port CON X1220 ...

Page 36: ...ol XILINX ChipScope to the XMC CPU Zulu connector X1410 NOTICE The connector X400 is for factory test only do not connect The adapter can be used by esd to connect X400 to a JTAG chain of the Health Controller and PCIe to PCI bridge Samtec CLM box header 8 pins 10 pins to X1410 Figure 7 XMC CPU ADAPTER FPGA NOTICE The 8 pole SMD strip has no inverse polarity protection Property damage may result d...

Page 37: ...connector X800 on the PCB bottom side of XMC CPU Zulu The socket strip can be connected to the XMC CPU Zulu Testadapter The JTAG Adapter comes with a 14 pos socket strip and a 14 pos header Socket strip and Header Figure 8 Socket strip Figure 9 Header Figure 10 XMC JTAG Adapter NOTICE The 14 pole SMD strips have no inverse polarity protection Property damage may result due to incorrect adapter con...

Page 38: ...ssignments Page 38 of 45 Hardware Manual Doc Nr V 2031 21 Rev 1 0 XMC CPU Zulu Connecting the XMC CPU Zulu Testadapter to the XMC CPU Zulu via XMC JTAG Adapter Figure 11 Connecting diagram of the XMC JTAG Adapter ...

Page 39: ...s from esd are available as described in the Order Information on page 45 The BSPs include an example source code for the FPGA Programming of the FPGAs is done via XILINX Toolchain See www xilinx com for further information Loading of the FPGA is done during the system Start up as part of loading the BOOT BIN image For the FPGA an esdACC esd Advanced CAN Controller implementation is available as c...

Page 40: ... homepage of the U Boot project is http www denx de wiki U Boot Update Mechanism Via Ethernet System Boot U Boot is configured in a way that the operating system can boot from different sources 1 SPI Flash 2 eMMC 3 SD card 4 USB 8 3 2 Operating System Operating system Peta Linux Author license holder XILINX Delivery Download Link Licenses Predominantly GPL a detailed listing of the licenses that m...

Page 41: ... components for the support of the A53 cores and not of the R5 CPUs which are also contained in the system A Boot Image BOOT BIN which is created with the toolchain usually contains the following components esd electronics assumes only a limited warranty for the necessary adjustments to the components in the scope of this project Name Short information Meaning Source Comment FSBL First stage bootl...

Page 42: ...e and necessary adaptions to the hardware are implemented A toolchain for building the U Boot image is provided After powering up the XMC CPU Zulu U Boot is started and can be operated via the console CON Following hardware components are supported by U Boot Hardware Description RS232 Used as console CON GPIO Only with example FPGA image Network PS based interfaces are supported SPI Access to SPI ...

Page 43: ...orted Test of the standard network functionality SPI Access to SPI memory uSD eMMC Storage media can be used as file system HEALTH Access on the temperature and voltage values partly via I2C LED Control of the tricolour LEDs PCIe The XMC CPU Zulu normally works as PCI endpoint and supports accesses from the PCI Master to a memory range of the XMC CPU Zulu and Master accesses to the memory of the H...

Page 44: ...Declaration of Conformity Page 44 of 45 Hardware Manual Doc Nr V 2031 21 Rev 1 0 XMC CPU Zulu 10 Declaration of Conformity ...

Page 45: ...rd Support Package incl 12 moths support V 2031 77 XMC CPU Zulu Linux BSP Bundle BSP Bundle including 1 Board Support Package V 2031 77 12 months Hotline Support and Linux BSP Updates V 2031 67 V 2031 57 Support for BSPs XMC CPU Zulu Linux Support Hotline Support and Linux BSP Updates for 12 months V 2031 67 For detailed information about the driver availability for your special operating system p...

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