Technical Data
ECS-CPCIs/FPGA
Hardware Manual Doc.-Nr.: E.1108.21/ 1.0
Page 21 of 28
Number
1
Standard
100BASE-TX, 100Mbit/s according to IEEE 802.3
Controller
EtherCAT Slave Controller Beckhoff IP Core integrated in FPGA
+ 2x MII Phy (Micrel KSZ8081MNX)
Electrical isolation
via transformer, integrated in RJ45 connectors
Ports
IN and OUT
Connector
2 x RJ45 socket with separate LEDs for status indication (see
page 16)
Table 7:
Data of the EtherCAT interface
Number
2 x Sync + 2 x Latch
Electrical isolation
none
Voltage level and
termination
3.3V LVTTL configured as 4 single ended lines, no protection against
electrostatic discharge or over voltage.
The lines include a 33 Ω series
resistors near to the FPGA.
On customer request the lines can be modified as two differential 2,5V
LVDS pairs (one sync and one latch function must be shifted to user I/O
lines then). Ask our sales team (
) for further information.
Controller
Integrated in FPGA
Connector
High Speed/Modular Connector (all signals on P3) (For the pin assignment
see chapter
“P3 – 96-Pin Header configured for LVTTL I/O” on page 25.)
Table 8:
Data of SYNC/LATCH interface on P3
Number
32 User I/O
Electrical isolation
None
Voltage Level and
Termination
3.3V LVTTL configured as single ended lines, no protection against
electrostatic discharge or over voltage.
16 lines include a
33 Ω-series resistor near to the FPGA. On customer
request these 16 lines can be modified as 8 differential 2,5V LVDS pairs.
Ask our sales team (
) for further information.
Controller
Integrated in FPGA
Power Supply
Output
3,3V/ 1A unprotected and 12V / 0,5A unprotected
Connector
High-Speed/Modular Connector (all signals on P3) (For the pin assignment
see chapter
“P3 – 96-Pin Header configured for LVTTL I/O” on page 25.)
Table 9:
Data of User-I/O interface on P3
4.4 EtherCAT Interface
4.5 SYNC / LATCH Interface on P3
4.6 User-I/O on P3
