LPF/DC/T/R SW Module (U8)
The output of the PA module is connected to
LPF/DC/SW. This network is a passive LC low-pass filter
with an insertion loss of less than 1.2 dB in the pass-band. It
also has a rejection greater than 50 dB in the stop band. The
output of this module is connected to the system antenna or
to the UDC connector.
Receive Circuit
The M-RK receive circuit, as shown in Figure 3, consists
of the following circuits:
•
RF Amplifier/Mixer
•
First If Amplifier
•
Second IF Amplifier/Discriminator
RF Amplifier/Mixer
The Rf Amplifier/Mixer circuit (Figure 8) contains two
third-order band-pass filters (FL301 and FL302), and RF
amplifier circuit (Q3O1) and a double-balanced diode mixer
circuit (Z2). RF from the antenna or UDC connector is cou-
pled through LPF/DC/TR SW module to the input of the RF
amplifier circuit. The RF signal on the input of the RF ampli-
fier is first coupled through band-pass filter FL301 to the in-
put of grounded emitter broad-band RF amplifier transistor
Q301. This amplifier provides 13 dB of power gain to reduce
thermal noise. The output of the RF amplifier is coupled
through band-pass filter FL3D2 to drive double balanced
mixer circuit Z2.
The RF signal from the RF amplifier and the injection
frequency from the synthesizer circuit, provide a 55.025
MHz IF on the output of the mixer. The double-balanced
Mixer has a typical conversion loss of 7.5 dB between the Rf
input and IF output. All inputs and the output of the RF Am-
plifier/Mixer have 50 ohms matching impedance. The +7
dBm injection frequency level, provided by the synthesizer
and amplifier circuit transistor Q103, is connected to the in-
jection frequency input. The output of the Mixer circuit is
connected to the input of the first IF Amplifier.
First IF Amplifier
The first IF amplifier contains a amplifier circuit and two
crystal filters of two poles, respectively (refer to Figure 7).
The first IF signal (55.025 MHz) connects to the input of
preamplifier transistor Q302 through pre-crystal filter FL303
with an impedance of approximately 3 Kohms. Pre-amplifier
Q302 provides a 23 dB power gain. The output is connected
to the input of IF amplifier IC U11 through crystal filter
FL304.
Second IF Amplifier/Discriminator (U11)
The Second IF Amplifier/Discriminator circuit (Figure
10) contains FM IF IC U11 (TA31132F) and 455 kHz ce-
ramic filter FL305, FL306, FL307. The FM IF IC contains a
local oscillator, mixer, IF amplifier, FM detector, and an
audio amplifier. The 55.025 MHz IF output from the first IF
amplifier is connected to the input of second IF amplifier
U11 pin 21 of TA31132F and converted to the second If fre-
quency (455 kHz). The second IF output is connected to pin
7 input of TA31132F through the 455 kHz ceramic filter to
the IF amplifier and FM detector circuits. The recovered
audio from the FM IF IC is connected to J1-3B.
Synthesizer Circuit
The Synthesizer circuit (Figure 11) contains
Phase-Lock-Loop (PLL) module U2, VCTCXO Reference
Oscillator module Z1, TX/RX Voltage Controlled Oscillator
(VCO) module U5, and a Low-Pass-Filter (LPF) amplifier.
The VCO used generate the receive and transmit frequencies
is locked to a stable VCTCXO reference oscillator through a
PLL. This feed-back loop divides the VCO frequency down
to a signal in the range of 3.5 MHz. This signal is divided
with a programmable divider to 6.25 kHz, and generates a
VCO control signal by comparing the 6.25 kHz feedback
with a 6.25 kHz signal derived by dividing a 13.2 MHz
VCTCXO by 2112. As the least-significant bit in the
programming is changed, the VCO is forced to change by
6.25 kHz.
The synthesizer circuitry is contained on two modules,
the VCO module U5 and the VCTCXO reference oscillator
module Z1.
Phase-Lock-Loop Module (U2)
The PLL module U2 contains a reference frequency, di-
vider, phase detector, and a programmable divider. The phase
detector dc voltage output signal is filtered with a passive
low-pass filter followed by a 6.25 kHz filter to reduce the
level of reference modulation on the VCO. This dc output
represents the error between the VCO frequency (phase) and
the reference (VCTCXO) and is applied to the VCO on fre-
quency. A lock-detect output is developed from pin 9 of U2.
The output is "AND"ed with the TX-PTT output from the
microcomputer to prevent transmission before the VCO is on
frequency.
Serial data from the microcomputer is shifted into the
PLL to set the division parameter which establishes the fre-
quency. A clock signal is provided on another input and the
data is latched with the enable input.
LBI-38735
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