Epson SED1751 Technical Manual Download Page 6 | Manualshive

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SED1751

5–4

EPSON

MLS Driver Chip Set

Technical Manual

VDDHL

GNDL

+V1L

VCL

–V1L

DOFF

GNDR

+V1R

VCR

–V1R

CIO2

LCD Driver: 120-bits

Level Shifter: 3x120-bits

Decoder

Bi-directional Shift Register: 30-bits

Data Register:

120-bits

VCC

TEST1

LP

YD

CIO1

COM 1

COM 120

SHL

SEL

LSEL

CSEL

FR

F1

F2

Block Diagram

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Summary of Contents for SED1751

Page 1: ...SED1751 ...

Page 2: ...SED1751 MLS Driver Chip Set EPSON i Technical Manual Contents OVERVIEW 5 1 TERMINAL FUNCTIONS 5 3 ABSOLUTE MAXIMUM RATINGS 5 9 ...

Page 3: ...fficiency for 1 240 and 1 480 duty panels Features LCD driver outputs 120 Low output ON resistance High duty drive supported 1 480 Reference value Broad range of LC drive voltages 14 to 42 V VCC 2 7 to 5 5 V Output shift direction pin select is possible Can be switched between 100 and 120 outputs Non biased display OFF function Logic system power source 2 7 V to 5 5 V LC power source offset bias c...

Page 4: ...R 5622 34 V1R 5717 35 VDDHR 5812 Pin Name X Y Pin Name X Y 36 COM1 5945 902 37 COM2 822 38 COM3 742 39 COM4 662 57 COM22 5945 778 58 COM23 5945 858 59 COM24 5945 938 60 COM25 5709 1034 61 COM26 5549 1034 62 COM27 5389 1034 93 COM58 429 1034 94 COM59 269 95 COM60 109 96 COM61 109 97 COM62 269 98 COM63 429 129 COM94 5389 1034 130 COM95 5549 1034 131 COM96 5709 1034 132 COM97 5945 938 133 COM98 5945 ...

Page 5: ...ode Select input for the number of COM output terminals SEL I 120 outputs 100 outputs 1 L COM1 to COM120 H COM9 to COM108 LSEL I 1 2 H operation select signal input 1 L Normal operation H 1 2 operation Chip select signal input for when a cascade connection CSEL I is used 1 L Leading chip H Other chips FR I LC drive output AC signal input With terminator 1 1 LC display blanking control input With a...

Page 6: ...l Manual VDDHL GNDL V1L VCL V1L DOFF GNDR V1R VCR V1R CIO2 LCD Driver 120 bits Level Shifter 3x120 bits Decoder Bi directional Shift Register 30 bits Data Register 120 bits VCC TEST1 LP YD CIO1 COM 1 COM 120 SHL SEL LSEL CSEL FR F1 F2 Block Diagram ...

Page 7: ...from a logic system level to the LC driver system voltage level LCD Driver The LCD driver outputs the LC drive voltage The relationship between the display blanking signal DOFF the field recognition signals F1 F2 the AC signal FR and the common output voltage is as follows DOFF H L FR L H F1 F2 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 Line 1 V1 V1 V1 V1 V1 V1 V1 V1 VC Line 2 V1 V1 V1 V1 V1 V1 V1 V1 VC Line...

Page 8: ...R LP Driver 1 COM1 V1 VC V1 COM2 V1 VC V1 COM3 V1 VC V1 COM4 V1 VC V1 COM5 V1 VC V1 COM6 V1 VC V1 COM7 V1 VC V1 COM8 V1 VC V1 Driver 2 COM120 Field 1 Field 2 Field 3 1 Frame 240 lines Field 4 1 2 3 60 61 62 63 120 121 122 123 180 181 182 183 240 1 2 3 1 1 2 3 4 5 30 31 32 33 60 61 62 63 90 91 92 93 120 121 122 123 2 3 4 5 240 lines 120 121 122 123 240 1 2 3 4 YD LP FR LP CIO 1 CIO 2 ...

Page 9: ...OM4 V1 VC V1 COM5 V1 VC V1 COM6 V1 VC V1 COM7 V1 VC V1 COM8 V1 VC V1 Driver 2 COM120 Field 1 Field 2 Field 3 1 Frame 240 lines Field 4 2 240 2 1 2 60 2 61 2 120 2 121 2 180 2 181 2 240 2 1 1 1 1 1 1 61 1 62 1 121 1 122 1 181 1 182 1 1 1 1 1 1 1 1 2 1 1 2 2 2 1 3 1 30 2 30 1 31 2 31 1 60 2 60 1 61 2 61 1 90 2 90 1 91 2 91 1 120 2 120 1 121 2 121 2 1 1 2 2 2 1 3 240 lines 1 120 2 120 1 121 2 121 2 2...

Page 10: ... 65 to 150 C Storage temperature 2 Tstg2 55 to 100 C NOTE 1 The voltages are all relative to GND 0 V NOTE 2 Storage temperature 1 is for the chip alone and storage temperature 2 is for the TCP product NOTE 3 Ensure that the relationship between V1 VC and V1 is always as follows VDDH V1 VC V1 GND NOTE 4 The LSI may be permanently damaged if the logic system power is floating or VCC is less than or ...

Page 11: ...age 0 3mA Input Leakage Current ILI GND VIN VCC 2 0 µA Input Output Leakage ILI O GND VIN VCC CIO1 CIO2 5 0 µA Current Static Current IGND VDDH 14 0 42 0V GND 25 µA VIH VCC VIL GND VON 0 5 V VDDH 0 55 0 7 Output Resistance RCOM Recommended 30 0V COM1 to kΩ parameter VDDH COM120 0 5 0 7 40 0V VCC 5 0 V VIH VCC VIL GND fLP 16 8 kHz 10 25 Average Operating fFR 70 Hz Consumption Current ICC Input data...

Page 12: ...anual Range of Operating Voltages VCC VDDH It is necessary to set the voltage for VDDH within the VCC VDDH operating voltage range shown in the diagram below Range of Operating Voltage 50 42 40 30 20 10 28 8 0 2 0 3 0 2 7 4 0 VCC V V DDH V 5 0 6 0 5 5 ...

Page 13: ...100 ns FR Hold Time tFRDH 40 F1 F2 Setup Time tFFDS 100 F1 F2 Hold Time tFFDH 40 Input Signal Rise Time tr 50 ns Input Signal Fall Time tf 50 ns CIO Setup Time tDS 100 ns CIO Hold Time tDH 40 ns YD LP Allowable Time tSET 80 ns VCC 2 7 V to 4 5 V Ta 30 to 85 C Item Signal Parameter Min Max Units LP Frequency tCCL 800 ns LP H Pulse Width tWCLH 100 ns LP L Pulse Width tWCLL 660 ns FR Setup Time tFRDS...

Page 14: ...me from LP to CIO output tpdDOC CL 15 pF 300 ns Delay time from LP to COM output tpdCCL VDDH 350 ns Delay time from DOFF to COM output tpdCDOF 14 0 V to 40 0 V 700 ns VCC 2 7 V to 4 5 V VDDH 14 0 to 28 0 V Ta 30 to 85 C Item Signal Parameter Min Max Units Delay time from LP to CIO output tpdDOC CL 15 pF 600 ns Delay time from LP to COM output tpdCCL VDDH 500 ns Delay time from DOFF to COM output t...

Page 15: ...CD system is high voltage if the logic system power supply of this LSI is floating or if VCC is 2 6 V or less when the LCD system high voltage 30 V or above is applied or if the LCD drive signal is output before the voltage level that is applied to the LCD system has stabilized then there is the risk that there will be an over current condition in this LSI resulting in permanent damage to this LSI...

Page 16: ...EL SEL SHL YSCL SHLL DL0 7 120 SED1751 CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1 F2 CIO2 120 SED1751 CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1 F2 CIO2 120 SED1751 CIO1 YD LP FR DOFF SHL SEL LSEL CSEL F1 F2 CIO2 120 SED1751 EIO2 D0 7 DOFF XSCL LP FR YD CA SHL F1S F2S F1O F2O LSEL BSEL EIO1 160 SED1580 EIO2 D0 7 DOFF XSCL LP FR YD CA SHL F1S F2S F1O F2O LSEL BSEL EIO1 160 SED1580 EIO2 D0 7 DOFF XSCL LP ...

Page 17: ...d be P1 coated Rear surface should be P1 coated Detail drawing for the test pad section Output terminal pattern shape Specifications Base Eupirex S 75 u m Copper foil 31P 14 25mm Sn plated Product pitch 31P 14 25mm Solder resist position tolerance 0 3 Molding range Molding range Rear surface should be P1 coated Molding range Molding range ...

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