LCD Interface Pin Mapping
S5U13706P00C100 Evaluation Board
Seiko Epson Corporation
15
Rev. 1.2
Note
1
When dip switch SW1-4 is open (CNF3 = 0 at RESET#), GPIO[6:0] are at low output
states after reset. If REG[10h] bits 1-0 are set for either HR-TFT or D-TFD, some
of the pins are used for the HR-TFT or D-TFD interfaces and are not available as
GPIO pins.
Table 5-2: Extended LCD Signal Connector (H2)
Pin
Name
Connector
Pin No.
Monochrome
Passive Panel
Color Passive Panel
Color TFT Panel
Single
Single
Others
HR-TFT
1
D-TFD
1
Format 1 Format 2
4-bit
8-bit
4-bit
8-bit
8-bit
16-Bit
9-bit
12-bit
18-bit
18-bit
18-bit
GPIO0
1
GPIO0
PS
XINH
GPIO1
3
GPIO1
CLS
YSCL
GPIO2
5
GPIO2
REV
FR
GPIO3
7
GPIO3
SPL
FRS
GPIO4
9
GPIO4
GPIO4
RES
GPIO5
11
GPIO5
GPIO5
DD_P1
GPIO6
13
GPIO6
GPIO6
YSCLD
CVOUT
15
CVOUT
GND
2, 4, 6, 8, 10,
12, 14, 16
GND
