S1R72104 Technical Manual
Rev.1.1
EPSON
29
7.5 Others and Cautions about Operation
Operation responding to the selection without SCSI-1 arbitration phase
The IC operates responding to the selection of only a target ID of SCSI-1 as mentioned below. Note that there
occurs no (automatic) transition to the message or command phase after selection, as in the usual cases after
Wait_selection command.
1
If only an ID is selected after Wait_select_cmd command was issued, IDERR interrupt occurs and the
command ends.
The inside is in the condition where connection is complete, though. So message_out/command_out and
other commands can be issued, as in the usual case the selection is made with an initiator/target ID.
(Except that message_out/command_out is not executed automatically.)
2
If an ID of 3 bits or more is selected, IDERR interrupt occurs. This distinguishes whether selection of 1
bit is completed or IDERR with an ID of 3 bits or more is selected.
If 1 bit is selected, IDERR and SEL interrupts occur. If ATN is not asserted here, WOATN interrupt
occurs, too.
* The firm is asked to check that SCSI-1 selection has occurred by observing SEL interrupt at the same timing
when IDERR interrupt occurs.
Also, issue message_out/command_out manually while observing the condition of WOATN interrupt,
because IDERR terminates Wait_selection command.
Parity error in SCSI data phase, or command stop operation by detection of ATN
Take note of the following points when port interface is used as slave:
If a setting has been made that a parity error or detection of ATN in SCSI data phase stops the operation of a
command (STATN/STPPE/SPCEN bit of SCSIMODE register), occurrence of such factor and subsequent
command stop cause negation of PDREQ being output to port interface at the internal timing of the IC.
Accordingly, use such setting after checking that it causes no problem in hand-shake on the LSI side connected
to the IC.
In such a case, no problem occurs in the internal sequence of the IC if XPDACK or XPRD/XPWR may come
from the port side. Though, data transfer to and from FIFO may be obstructed depending on timing.
(The data may not be written in or read from the FIFO.)
In such a case, the FIFO terminates in uncompleted manner, so it requires clearing before going to the status
phase.
