9. REFERENCE: EXTERNAL CONNECTION EXAMPLES
S1F76540M0C Series Technical Manual
EPSON
25
(Rev.1.1)
9.7 Parallel Connection (Boosting Capacity Increase)
The parallel connection is effective when lowering the boosting output impedance or reducing the ripple voltage.
Connecting n S1F76540s in parallel sets the boosting output impedance to approximately 1/n. Only the
smoothing capacitor CO for boosting output can be shared even in parallel connection.
Using the regulator allows you to operate only one of n S1F76540s that are connected in parallel. (Running
multiple regulators in parallel will generate the reactive consumption current.)
Figure 9.8 shows a “quadruple bo regulator” connection example where two S1F76540s are connected
in parallel.
Master IC
Slave
IC
Figure 9.8 Parallel connection example
Figure 9.8 Setting conditions
Master IC
Slave IC
Internal clock
: ON (Low output mode)
Internal clock : OFF (Clocks supplied from master IC)
Booster
:
ON
Booster
: ON
Regulator
:
OFF
Regulator
: ON (Select CT0 = -0.05
%
/
°
C.)
Power-off method
In the connection example shown in Figure 9.8, setting S1F76540 in the master IC to POFF2X = L (VI)
enables you to stop boosting the master and slave ICs; however, the regulator in the slave IC does not stop.
When
|
V
REG
|
is greater than
|
VI
|
, the voltage that is equivalent to VI is generated in the V
REG
pin.
When placing the V
REG
pin into the high impedance state, set both the master and slave ICs to POFF1X = L
and POFF2X = L.
Other setting conditions
(1) When using the high output mode
Connect the FC pin in the master IC to VI.
(2) When changing the temperature coefficient CT
Change the TC1 and TC2 pins in the slave IC as shown in Table 5.3.
C3’
+
R1
R2
VO
VRI
V
REG
RV
V
DD
FC
TC1
TC2
C2P
C2N
C3N
C1N
C1P
VI
POFF1X
POFF2X
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
1
C2’
+
C1’
+
CREG
+
V
REG
V
DD
VO
VRI
V
REG
RV
V
DD
FC
TC1
TC2
C2P
C2N
C3N
C1N
C1P
VI
POFF1X
POFF2X
2
3
4
5
6
7
8
10
9
11
12
13
14
15
16
1
C2
+
C3
+
C1
+
CI
+
CO
+
VI
