Epson S1C31D50, Technical Instructions

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8-2
Seiko Epson Corporation
S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
8.3. Control Registers
P xy – xz Universal Port Multiplexer Setting Register
Register name Bit Bit name Initial Reset R/W Remarks
UPMUXP x MUX n 15 – 13 P xz PPFNC[2:0] 0x0 H0 R/W –
12 – 11 P xz PERICH[1:0] 0x0 H0 R/W
10 – 8 P xz PERISEL[2:0] 0x0 H0 R/W
7 – 5 P xy PPFNC[2:0] 0x0 H0 R/W
4 – 3 P xy PERICH[1:0] 0x0 H0 R/W
2 – 0 P xy PERISEL[2:0] 0x0 H0 R/W
*1: ‘ x ’ in the register name refers to a port group number and ‘ n ’ refers to a register number (0 – 3).
*2: ‘ x ’ in the bit name refers to a port group number, ‘ y ’ refers to an even port number (0, 2, 4, 6), and ‘ z ’ refers to an
odd port number ( z = y + 1).
Bits 15 – 13 P xz PPFNC[2:0]
Bits 7 – 5 P xy PPFNC[2:0]
These bits specify the peripheral I/O function to be assigned to the port. (See Table 8.3.1.)
Bits 12 – 11 P xz PERICH[1:0]
Bits 4 – 3 P xy PERICH[1:0]
These bits specify a peripheral circuit channel number. (See Table 8.3.1.)
Bits 10 – 8 P xz PERISEL[2:0]
Bits 2 – 0 P xy PERISEL[2:0]
These bits specify a peripheral circuit. (See Table 8.3.1.)
Table 8.3.1 Peripheral I/O Function Selections
UPMUXP x MUX n .
P xy PPFNC[2:0] bits
(Peripheral I/O
function)
UPMUXP x MUX n .P xy PERISEL[2:0] bits (Peripheral circuit)
0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
None * I2C SPIA UART3 T16B Reserved Reserved Reserved
UPMUXP x MUX n .P xy PERICH[1:0] bits (Peripheral circuit channel)
– 0x0 – 0x1 0x0 0x0 – 0x2 0x0 – 0x1 – – –
– Ch.0 – 2 Ch.0-2 Ch.0 – 2 Ch.0 – 1 – – –
0x0 None * None * None * None * None * None * None * None *
0x1
Reserved
SCL n SDI n USIN n
TOUT n 0/
CAP n 0
Reserved Reserved Reserved
0x2 SDA n SDO n USOUT n
TOUT n 1/
CAP n 1
0x3
Reserved
SPICLK n
Reserved
TOUT n 2/
CAP n 2
0x4 #SPISS n
TOUT n 3/
CAP n 3
0x5
Reserved
Reserved
0x6 Reserved
0x7 Reserved
*
“None” means no assignment. Selecting this will put the P xy pin into Hi-Z status when peripheral I/O function 1 is
selected and enabled in the I/O port.
Note:
Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the
same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due
to the internal delay.